[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev7)
URL   : https://patchwork.freedesktop.org/series/103491/
State : warning

== Summary ==

Error: dim checkpatch failed
fc068ba78c19 drm/i915: Relocate intel_crtc_dotclock()
21a52257a3d5 drm/i915: Shuffle some PLL code around
c98adf166f76 drm/i915: Extract HAS_DOUBLE_BUFFERED_M_N()
-:53: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#53: FILE: drivers/gpu/drm/i915/i915_drv.h:871:
+#define HAS_DOUBLE_BUFFERED_M_N(dev_priv)	(DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))

-:53: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#53: FILE: drivers/gpu/drm/i915/i915_drv.h:871:
+#define HAS_DOUBLE_BUFFERED_M_N(dev_priv)	(DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))

total: 0 errors, 1 warnings, 1 checks, 25 lines checked
3b92e000702a drm/i915/dsi: Extract {vlv, bxt}_get_pclk()
bb595ece9630 drm/i915: Do .crtc_compute_clock() earlier
915847ac09ba drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
c611a1bf92c2 drm/i915: Feed the DPLL output freq back into crtc_state
07578c0aebe6 drm/i915: Compute clocks earlier
fad8836005f0 drm/i915: Make M/N checks non-fuzzy
951939e868fe drm/i915: Make all clock checks non-fuzzy
f85fb3730e57 drm/i915: Set active dpll early for icl+
b6814d247c3f drm/i915: Nuke fastet state copy hacks
3cad35b9065e drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled
24cfad91c112 drm/i915: Add intel_panel_highest_mode()
84ff5137845b drm/i915: Allow M/N change during fastset on bdw+
8206cbd75216 drm/i915: Use a fixed N value always
5cff60f330cb drm/i915: Round TMDS clock to nearest