[Intel-gfx] [PATCH v5 2/5] drm/i915: Parse and set stepping for platforms with GMD

[Matt Roper]

On Tue, Sep 13, 2022 at 11:33:38AM -0700, Radhakrishna Sripada wrote:
> From: José Roberto de Souza <jose.souza at intel.com>
> 
> The GMD step field do not properly match the current stepping convention
> that we use(STEP_A0, STEP_A1, STEP_B0...).
> 
> One platform could have { arch = 12, rel = 70, step = 1 } and the
> actual stepping is STEP_B0 but without the translation of the step
> field would mean STEP_A1.
> That is why we will need to have gmd_to_intel_step tables for each IP.

I think you might have missed my feedback on v4:

        https://patchwork.freedesktop.org/patch/500850/?series=106786&rev=8#comment_904487

Can we just handle this in a standard way, at least until we come across
a future platform that breaks from the current standard and needs a
special exception?


Matt

> 
> v2:
>  - Pass the updated ip version structure
> 
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_step.c | 60 +++++++++++++++++++++++++++++++
>  1 file changed, 60 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index 42b3133d8387..bc966478f0f8 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -135,6 +135,48 @@ static const struct intel_step_info adlp_n_revids[] = {
>  	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
>  };
>  
> +struct gmd_to_intel_step {
> +	struct ip_version gmd;
> +	enum intel_step step;
> +};
> +
> +static const struct gmd_to_intel_step gmd_graphics_table[] = {
> +	{ .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 },
> +	{ .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 },
> +	{ .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 0, .step = STEP_A0 },
> +	{ .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 4, .step = STEP_B0 },
> +	{ .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 0, .step = STEP_A0 },
> +	{ .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 4, .step = STEP_B0 },
> +};
> +
> +static const struct gmd_to_intel_step gmd_media_table[] = {
> +	{ .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 },
> +	{ .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 },
> +};
> +
> +static const struct gmd_to_intel_step gmd_display_table[] = {
> +	{ .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 0, .step = STEP_A0 },
> +	{ .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 4, .step = STEP_B0 },
> +};
> +
> +static u8 gmd_to_intel_step(struct drm_i915_private *i915,
> +			    struct ip_version *gmd,
> +			    const struct gmd_to_intel_step *table,
> +			    int len)
> +{
> +	int i;
> +
> +	for (i = 0; i < len; i++) {
> +		if (table[i].gmd.ver == gmd->ver &&
> +		    table[i].gmd.rel == gmd->rel &&
> +		    table[i].gmd.step == gmd->step)
> +			return table[i].step;
> +	}
> +
> +	drm_dbg(&i915->drm, "Using future steppings\n");
> +	return STEP_FUTURE;
> +}
> +
>  static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
>  
>  void intel_step_init(struct drm_i915_private *i915)
> @@ -144,6 +186,24 @@ void intel_step_init(struct drm_i915_private *i915)
>  	int revid = INTEL_REVID(i915);
>  	struct intel_step_info step = {};
>  
> +	if (HAS_GMD_ID(i915)) {
> +		step.graphics_step = gmd_to_intel_step(i915,
> +						       &RUNTIME_INFO(i915)->graphics.ip,
> +						       gmd_graphics_table,
> +						       ARRAY_SIZE(gmd_graphics_table));
> +		step.media_step = gmd_to_intel_step(i915,
> +						    &RUNTIME_INFO(i915)->media.ip,
> +						    gmd_media_table,
> +						    ARRAY_SIZE(gmd_media_table));
> +		step.display_step = gmd_to_intel_step(i915,
> +						      &RUNTIME_INFO(i915)->display.ip,
> +						      gmd_display_table,
> +						      ARRAY_SIZE(gmd_display_table));
> +		RUNTIME_INFO(i915)->step = step;
> +
> +		return;
> +	}
> +
>  	if (IS_PONTEVECCHIO(i915)) {
>  		pvc_step_init(i915, revid);
>  		return;
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation