[Intel-gfx] [PATCH 17/19] drm/i915/perf: Save/restore EU flex counters across reset

[Dixit, Ashutosh]

On Tue, 23 Aug 2022 13:41:53 -0700, Umesh Nerlige Ramappa wrote:
>
> If a drm client is killed, then hw contexts used by the client are reset
> immediately. This reset clears the EU flex counter configuration. If an
> OA use case is running in parallel, it would start seeing zeroed eu
> counter values following the reset even if the drm client is restarted.
> Save/restore the EU flex counter config so that the EU counters can be
> monitored continuously across resets.

Reviewed-by: Ashutosh Dixit <ashutosh.dixit at intel.com>

Not sure if this needs to be done for non-GuC (execlists) too? Anyway
that's a later patch.

> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 74cbe8eaf531..3e152219fcb2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -375,6 +375,14 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
>	for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++)
>		ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
>
> +	ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL0, false);
> +	ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL1, false);
> +	ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL2, false);
> +	ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL3, false);
> +	ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL4, false);
> +	ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL5, false);
> +	ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL6, false);
> +
>	return ret ? -1 : 0;
>  }
>
> --
> 2.25.1
>