[Intel-gfx] [PATCH v4.1] drm/i915/mtl: Define engine context layouts

[Lucas De Marchi]

On Wed, Sep 28, 2022 at 08:55:11AM -0700, Radhakrishna Sripada wrote:
>From: Matt Roper <matthew.d.roper at intel.com>
>
>The part of the media and blitter engine contexts that we care about for
>setting up an initial state on MTL are nearly similar to DG2 (and PVC).
>The difference being PRT_BB_STATE being replaced with NOP.
>
>For render/compute engines, the part of the context images are nearly
>the same, although the layout had a very slight change --- one POSH
>register was removed and the placement of some LRI/noops adjusted
>slightly to compensate.
>
>v2:
> - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> - Add missing nop in xcs offsets(Bala)
>v3:
> - Fix the spacing for nop in xcs offset(MattR)
>v4:
> - Fix rcs register offset(MattR)
>v4.1:
> - Fix commit message(Lucas)
>
>Bspec: 46261, 46260, 45585
>Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
>Cc: Licas De Marchi <lucas.demarchi at intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi