[Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

[Andi Shyti]

Hi Fei,

On Sun, Apr 16, 2023 at 11:25:02PM -0700, fei.yang at intel.com wrote:
> From: Fei Yang <fei.yang at intel.com>
> 
> Currently the KMD is using enum i915_cache_level to set caching policy for
> buffer objects. This is flaky because the PAT index which really controls
> the caching behavior in PTE has far more levels than what's defined in the
> enum. In addition, the PAT index is platform dependent, having to translate
> between i915_cache_level and PAT index is not reliable, and makes the code
> more complicated.
> 
> >From UMD's perspective there is also a necessity to set caching policy for

you have an extra '>' here.

> performance fine tuning. It's much easier for the UMD to directly use PAT
> index because the behavior of each PAT index is clearly defined in Bspec.
> Haivng the abstracted i915_cache_level sitting in between would only cause

/Haivng/Having/

> more ambiguity.
> 
> For these reasons this patch replaces i915_cache_level with PAT index. Also
> note, the cache_level is not completely removed yet, because the KMD still
> has the need of creating buffer objects with simple cache settings such as
> cached, uncached, or writethrough. For these simple cases, using cache_level
> would help simplify the code.
> 
> Cc: Chris Wilson <chris.p.wilson at linux.intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Fei Yang <fei.yang at intel.com>

fiuuuuu... quite a run this patch! But I did review it once,
anyway I checked it again, it looks all correct.

Reviewed-by: Andi Shyti <andi.shyti at linux.intel.com> 

Andi