[Intel-gfx] [PATCH 07/15] drm/i915: Use REG_BIT() & co. for ilk+ pfit registers

[Jani Nikula]

On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Polish the ilk+ pfit registers with REG_BIT() & co., and
> also take the opportunity to unify the ivb/hsw vs. not checks
> in ilk_pfit_enable() and ilk_get_pfit_config().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  9 +++++++--
>  drivers/gpu/drm/i915/i915_reg.h              | 20 ++++++++++----------
>  2 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ea1b0e87ae35..e9000ed15e7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3230,11 +3230,17 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 ctl, pos, size;
> +	enum pipe pipe;
>  
>  	ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
>  	if ((ctl & PF_ENABLE) == 0)
>  		return;
>  
> +	if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
> +		pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);
> +	else
> +		pipe = crtc->pipe;
> +
>  	crtc_state->pch_pfit.enabled = true;
>  
>  	pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
> @@ -3249,8 +3255,7 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
>  	 * ivb/hsw (since we don't use the higher upscaling modes which
>  	 * differentiates them) so just WARN about this case for now.
>  	 */
> -	drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
> -		    (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
> +	drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
>  }
>  
>  static bool ilk_get_pipe_config(struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eea739e0b48a..3c02f6c70733 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4008,16 +4008,16 @@
>  
>  /* CPU panel fitter */
>  /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
> -#define _PFA_CTL_1               0x68080
> -#define _PFB_CTL_1               0x68880
> -#define  PF_ENABLE              (1 << 31)
> -#define  PF_PIPE_SEL_MASK_IVB	(3 << 29)
> -#define  PF_PIPE_SEL_IVB(pipe)	((pipe) << 29)
> -#define  PF_FILTER_MASK		(3 << 23)
> -#define  PF_FILTER_PROGRAMMED	(0 << 23)
> -#define  PF_FILTER_MED_3x3	(1 << 23)
> -#define  PF_FILTER_EDGE_ENHANCE	(2 << 23)
> -#define  PF_FILTER_EDGE_SOFTEN	(3 << 23)
> +#define _PFA_CTL_1		0x68080
> +#define _PFB_CTL_1		0x68880
> +#define   PF_ENABLE			REG_BIT(31)
> +#define   PF_PIPE_SEL_MASK_IVB		REG_GENMASK(30, 29) /* ivb/hsw */
> +#define   PF_PIPE_SEL_IVB(pipe)		REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe))
> +#define   PF_FILTER_MASK		REG_GENMASK(24, 23)
> +#define   PF_FILTER_PROGRAMMED		REG_FIELD_PREP(PF_FILTER_MASK, 0)
> +#define   PF_FILTER_MED_3x3		REG_FIELD_PREP(PF_FILTER_MASK, 1)
> +#define   PF_FILTER_EDGE_ENHANCE	REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2)
> +#define   PF_FILTER_EDGE_SOFTEN		REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
>  #define _PFA_WIN_SZ		0x68074
>  #define _PFB_WIN_SZ		0x68874
>  #define _PFA_WIN_POS		0x68070

-- 
Jani Nikula, Intel Open Source Graphics Center