[Intel-gfx] [PATCH v3 12/12] vfio/pci: Report dev_id in VFIO_DEVICE_GET_PCI_HOT_RESET_INFO
Alex Williamson
alex.williamson at redhat.com
Wed Apr 26 13:20:20 UTC 2023
On Wed, 26 Apr 2023 07:22:17 +0000
"Liu, Yi L" <yi.l.liu at intel.com> wrote:
> > From: Alex Williamson <alex.williamson at redhat.com>
> > Sent: Thursday, April 20, 2023 10:09 PM
> [...]
> > > > Whereas dev-id < 0
> > > > (== -1) is an affected device which prevents hot-reset, ex. an un-owned
> > > > device, device configured within a different iommufd_ctx, or device
> > > > opened outside of the vfio cdev API." Is that about right? Thanks,
> > >
> > > Do you mean to have separate err-code for the three possibilities? As
> > > the devid is generated by iommufd and it is u32. I'm not sure if we can
> > > have such err-code definition without reserving some ids in iommufd.
> >
> > Yes, if we're going to report the full dev-set, I think we need at
> > least two unique error codes or else the user has no way to determine
> > the subset of invalid dev-ids which block the reset. I think Jason is
> > proposing the set of valid dev-ids are >0, a dev-id of zero indicates
> > some form of non-blocking, while <0 (or maybe specifically -1)
> > indicates a blocking device. I was trying to get consensus on a formal
> > definition of each of those error codes in my previous reply. Thanks,
>
> Seems like RESETTABLE flag is not needed if we report -1 for the devices
> that block hotreset. Userspace can deduce if the calling device is resettable
> or not by checking if there is any -1 in the affected device list.
There is some redundancy there, yes. Given the desire for a null array
on the actual reset ioctl I assumed there would also be a desire to
streamline the info ioctl such that userspace isn't required to parse
the return array, for example maybe userspace isn't required to pass a
full buffer and can get the reset availability status from only the
header. Of course it's still the responsibility of userspace to know
the extent of the reset. Thanks,
Alex
More information about the Intel-gfx
mailing list