[Intel-gfx] [PATCH 13/13] drm/i915/psr: Re-enable PSR1 on hdw/bdw

[Hogander, Jouni]

On Fri, 2023-04-28 at 14:36 +0300, Ville Syrjälä wrote:
> On Fri, Apr 28, 2023 at 11:19:39AM +0000, Hogander, Jouni wrote:
> > On Fri, 2023-04-21 at 15:03 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > 
> > > All known issues fixed now, so re-enable PSR1 on hsw/bdw.
> > 
> > Please note s/hdw/hsw/ in subject.
> > 
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_pci.c | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c
> > > index 272a8ba37b64..923e24044967 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -562,6 +562,8 @@ static const struct intel_device_info
> > > vlv_info =
> > > {
> > >                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
> > >         .display.has_ddi = 1, \
> > >         .display.has_fpga_dbg = 1, \
> > > +       .display.has_psr = 1, \
> > > +       .display.has_psr_hw_tracking = 1, \
> > 
> > Isn't this has_psr_hw_tracking about PSR2 with hw tracking
> > mechanism in
> > e.g. ICL? See Bspec: 4289. More recent platforms have manual
> > tracking
> > mechanism. In TGL there were both.
> 
> I have no idea what people meant by hw tracking in this context.
> psr_force_hw_tracking_exit() is the thing that does the
> CURSURFLIVE write to force PSR exit/etc. and that is used for
> PSR1 and PSR2. So someone should properly document what this is
> supposed to indicate, and rename either that function or this
> flag to refelct reality.

Ok, anyways this variable seems to be taken into account only in PSR2
context so this should not cause any problems either.

> 
> > 
> > >         .display.has_dp_mst = 1, \
> > >         .has_rc6p = 0 /* RC6p removed-by HSW */, \
> > >         HSW_PIPE_OFFSETS, \
> > > @@ -665,8 +667,6 @@ static const struct intel_device_info
> > > chv_info =
> > > {
> > >         .has_gt_uc = 1, \
> > >         .__runtime.has_hdcp = 1, \
> > >         .display.has_ipc = 1, \
> > > -       .display.has_psr = 1, \
> > > -       .display.has_psr_hw_tracking = 1, \
> > >         .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path
> > > allocation */ \
> > >         .display.dbuf.slice_mask = BIT(DBUF_S1)
> > >  
> > 
> > BR,
> > 
> > Jouni Högander
>