[Intel-gfx] [PATCH] drm/i915/vdsc: Fix first_line_bpg_offset calculation

[Tseng, William]

For DSC 1.1, the value is set to 12 at 8bpp and 8bpc if looking the table 
rc_parameters_pre_scr defined in drm_dsc_helper.c.  If slice_hiegith is 40,
the calculation result is 14, which is different from the value set in the table.
And the experiment result shows value 14 is not working for such DSI panel.

-----Original Message-----
From: Nautiyal, Ankit K <ankit.k.nautiyal at intel.com> 
Sent: Friday, August 4, 2023 3:55 PM
To: Kandpal, Suraj <suraj.kandpal at intel.com>; intel-gfx at lists.freedesktop.org
Cc: Tseng, William <william.tseng at intel.com>; Heikkila, Juha-pekka <juha-pekka.heikkila at intel.com>
Subject: Re: [PATCH] drm/i915/vdsc: Fix first_line_bpg_offset calculation


On 8/3/2023 9:32 PM, Suraj Kandpal wrote:
> On checking DSC1.1 Errata and DSC 1.2 spec the current formula we were 
> using was incorrect to calculate first_line_bpg_offset.
> The new fixed formula is derived from C model.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vdsc.c | 15 ++++++++++++---
>   1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c 
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 9d76c2756784..a344c6ab8767 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -65,6 +65,9 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
>   		intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420);
>   }
>   
> +#define CLAMP_TO(val, _min, _max) \
> +	max(_min, min(val, _max))

lets use clamp(), already defined in linux/minmax.h

With that fixed, this is:

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

> +
>   /*
>    * We are using the method provided in DSC 1.2a C-Model in codec_main.c
>    * Above method use a common formula to derive values for any 
> combination of DSC @@ -80,13 +83,19 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
>   	int bpc = vdsc_cfg->bits_per_component;
>   	int bpp = vdsc_cfg->bits_per_pixel >> 4;
>   	int qp_bpc_modifier = (bpc - 8) * 2;
> +	int uncompressed_bpg_rate;
> +	int first_line_bpg_offset;
>   	u32 res, buf_i, bpp_i;
>   
>   	if (vdsc_cfg->slice_height >= 8)
> -		vdsc_cfg->first_line_bpg_offset =
> -			12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
> +		first_line_bpg_offset =
> +			12 + (9 * min(34, vdsc_cfg->slice_height - 8)) / 100;
>   	else
> -		vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
> +		first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
> +
> +	uncompressed_bpg_rate = (3 * bpc + (vdsc_cfg->convert_rgb ? 0 : 2)) * 3;
> +	vdsc_cfg->first_line_bpg_offset = CLAMP_TO(first_line_bpg_offset, 0,
> +						   uncompressed_bpg_rate - 3 * bpp);
>   
>   	/*
>   	 * According to DSC 1.2 spec in Section 4.1 if native_420 is set: