[Intel-gfx] [PATCH] drm/i915/skl+: Disable DC states on DSI ports

Imre Deak imre.deak at intel.com
Fri Aug 11 15:38:54 UTC 2023


DC*co/5/6 is not supported on DSI ports active in video mode (Bspec
4234, 49193).

On GLK for DSI command mode the "Enter/Exit Low Power Mode" sequence
would need to be programmed around each frame update (Bspec 21356) and
presumedly the same is required on BXT and SKL, even though it's not
stated for those explicitly (BXT: Bspec 13756). The driver doesn't run
these sequences, but command mode on BXT-GLK is not implemented either.

On ICL+ for DSI command mode DC*co/DSI is supported by the HW (Bspec
49195), but this is not implemented in the driver.

Based on the above disable DC states while DSI ports are active.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/8419
Cc: <stable at vger.kernel.org>
Signed-off-by: Imre Deak <imre.deak at intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power_map.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 5ad04cd42c158..1950dae4a7649 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -331,6 +331,7 @@ I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2,
 
 I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
 	SKL_PW_2_POWER_DOMAINS,
+	POWER_DOMAIN_PORT_DSI,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_MODESET,
 	POWER_DOMAIN_GT_IRQ,
@@ -435,6 +436,7 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2,
 
 I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
 	BXT_PW_2_POWER_DOMAINS,
+	POWER_DOMAIN_PORT_DSI,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_GMBUS,
 	POWER_DOMAIN_MODESET,
@@ -517,6 +519,7 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2,
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
 	GLK_PW_2_POWER_DOMAINS,
+	POWER_DOMAIN_PORT_DSI,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_GMBUS,
 	POWER_DOMAIN_MODESET,
@@ -684,6 +687,7 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2,
 
 I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
 	ICL_PW_2_POWER_DOMAINS,
+	POWER_DOMAIN_PORT_DSI,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_MODESET,
 	POWER_DOMAIN_DC_OFF,
@@ -858,6 +862,7 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2,
 
 I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
 	TGL_PW_3_POWER_DOMAINS,
+	POWER_DOMAIN_PORT_DSI,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
@@ -1056,6 +1061,7 @@ I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3,
 
 I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
 	RKL_PW_3_POWER_DOMAINS,
+	POWER_DOMAIN_PORT_DSI,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_MODESET,
@@ -1138,6 +1144,7 @@ I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3,
 
 I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
 	DG1_PW_3_POWER_DOMAINS,
+	POWER_DOMAIN_PORT_DSI,
 	POWER_DOMAIN_AUDIO_MMIO,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
-- 
2.37.2



More information about the Intel-gfx mailing list