[Intel-gfx] [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates

[Kahola, Mika]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi at intel.com>
> Sent: Wednesday, August 23, 2023 8:08 PM
> To: intel-xe at lists.freedesktop.org; intel-gfx at lists.freedesktop.org
> Cc: Lisovskiy, Stanislav <stanislav.lisovskiy at intel.com>; Kahola, Mika <mika.kahola at intel.com>; De Marchi, Lucas
> <lucas.demarchi at intel.com>
> Subject: [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates
> 
> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> 
> According to BSpec we need to write the MBUS CTL and DBUF CTL both for increasing CDCLK case (pre plane) and for decreasing
> CDCLK case (post plane). Make sure those updates are in place for Xe2-LPD.
> 
> Since the mbus update is not only on pre-enable anymore, also rename the function accordingly.
> 
> Cc: Mika Kahola <mika.kahola at intel.com>

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 79454b4d99e3..77a4c85538c2 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3493,7 +3493,7 @@ static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>   * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
>   * update the request state of all DBUS slices.
>   */
> -static void update_mbus_pre_enable(struct intel_atomic_state *state)
> +static void update_mbus(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	u32 mbus_ctl, dbuf_min_tracker_val;
> @@ -3552,7 +3552,7 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> 
>  	WARN_ON(!new_dbuf_state->base.changed);
> 
> -	update_mbus_pre_enable(state);
> +	update_mbus(state);
>  	gen9_dbuf_slices_update(i915,
>  				old_dbuf_state->enabled_slices |
>  				new_dbuf_state->enabled_slices);
> @@ -3574,6 +3574,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> 
>  	WARN_ON(!new_dbuf_state->base.changed);
> 
> +	if (DISPLAY_VER(i915) >= 20)
> +		update_mbus(state);
> +
>  	gen9_dbuf_slices_update(i915,
>  				new_dbuf_state->enabled_slices);
>  }
> --
> 2.40.1