[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Convert link bitrate to clock

Patchwork patchwork at emeril.freedesktop.org
Mon Dec 4 19:10:59 UTC 2023


== Series Details ==

Series: drm/i915/display: Convert link bitrate to clock
URL   : https://patchwork.freedesktop.org/series/127287/
State : warning

== Summary ==

Error: dim checkpatch failed
1a78eb50da55 drm/i915/display: Move C20 HW readout
-:95: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#95: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2459:
+	cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;

-:110: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#110: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2474:
+			pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,

-:113: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#113: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2477:
+			pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,

-:121: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#121: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2485:
+				pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,

-:122: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#122: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2486:
+									  PHY_C20_B_MPLLB_CNTX_CFG(i));

-:124: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#124: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2488:
+				pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,

-:125: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#125: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2489:
+									  PHY_C20_A_MPLLB_CNTX_CFG(i));

-:131: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#131: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2495:
+				pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,

-:132: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#132: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2496:
+									  PHY_C20_B_MPLLA_CNTX_CFG(i));

-:134: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#134: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2498:
+				pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,

-:135: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#135: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2499:
+									  PHY_C20_A_MPLLA_CNTX_CFG(i));

total: 0 errors, 11 warnings, 0 checks, 128 lines checked
d9b0b0b350b3 drm/i915/display: Convert link bitrate to corresponding PLL clock
-:110: ERROR:POINTER_LOCATION: "(foo*)" should be "(foo *)"
#110: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3179:
+	intel_cx0pll_readout_hw_state(encoder, (struct intel_crtc_state*)new_crtc_state,

total: 1 errors, 0 warnings, 0 checks, 102 lines checked
525429c422fe drm/i915/display: Print out debug messages for clock rates




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