[PATCH 0/3] Cleanup C20 pll state

[Radhakrishna Sripada]

C20 pll state has both link_bit_rate and clock fields to represent
the clocks. Both have the same values for DP 1.4 they difer for
DP2.0. Stick to the numbers that are compatible with other clock
numbers like the port_clock in crtc_state

Radhakrishna Sripada (3):
  drm/i915/mtl: Use port clock compatible numbers for C20 phy
  drm/i915/mtl: Remove misleading "clock" field from C20 pll_state
  drm/i915/mtl: Rename the link_bit_rate to clock in C20 pll_state

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 79 ++++++++-----------
 .../drm/i915/display/intel_display_types.h    |  1 -
 2 files changed, 31 insertions(+), 49 deletions(-)

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2.34.1