[PATCH 2/3] drm/i915/mtl: Remove misleading "clock" field from C20 pll_state

Kahola, Mika mika.kahola at intel.com
Fri Dec 8 12:00:02 UTC 2023


> -----Original Message-----
> From: Sripada, Radhakrishna <radhakrishna.sripada at intel.com>
> Sent: Friday, December 8, 2023 12:10 AM
> To: intel-gfx at lists.freedesktop.org
> Cc: Sripada, Radhakrishna <radhakrishna.sripada at intel.com>; Taylor, Clinton A <clinton.a.taylor at intel.com>; Kahola, Mika
> <mika.kahola at intel.com>
> Subject: [PATCH 2/3] drm/i915/mtl: Remove misleading "clock" field from C20 pll_state
> 
> The field link_bit_rate serves as the actual clock value for the C20 pll_state structure. Remove the misleading clock field. The
> subsequent patch would rename the link_bit_rate as the clock field.
> 
> Cc: Clint Taylor <clinton.a.taylor at intel.com>
> Cc: Mika Kahola <mika.kahola at intel.com>

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c   | 18 ------------------
>  .../gpu/drm/i915/display/intel_display_types.h |  3 +--
>  2 files changed, 1 insertion(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 7d412be996ea..d518b55d5150 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -746,7 +746,6 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
>  /* C20 basic DP 1.4 tables */
>  static const struct intel_c20pll_state mtl_c20_dp_rbr = {
>  	.link_bit_rate = 162000,
> -	.clock = 162000,
>  	.tx = {	0xbe88, /* tx cfg0 */
>  		0x5800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -772,7 +771,6 @@ static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> 
>  static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
>  	.link_bit_rate = 270000,
> -	.clock = 270000,
>  	.tx = {	0xbe88, /* tx cfg0 */
>  		0x4800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -798,7 +796,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> 
>  static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
>  	.link_bit_rate = 540000,
> -	.clock = 540000,
>  	.tx = {	0xbe88, /* tx cfg0 */
>  		0x4800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -824,7 +821,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> 
>  static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
>  	.link_bit_rate = 810000,
> -	.clock = 810000,
>  	.tx = {	0xbe88, /* tx cfg0 */
>  		0x4800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -851,7 +847,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
>  /* C20 basic DP 2.0 tables */
>  static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
>  	.link_bit_rate = 1000000, /* 10 Gbps */
> -	.clock = 312500,
>  	.tx = {	0xbe21, /* tx cfg0 */
>  		0x4800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -876,7 +871,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> 
>  static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
>  	.link_bit_rate = 1350000, /* 13.5 Gbps */
> -	.clock = 421875,
>  	.tx = {	0xbea0, /* tx cfg0 */
>  		0x4800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -902,7 +896,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> 
>  static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
>  	.link_bit_rate = 2000000, /* 20 Gbps */
> -	.clock = 625000,
>  	.tx = {	0xbe20, /* tx cfg0 */
>  		0x4800, /* tx cfg1 */
>  		0x0000, /* tx cfg2 */
> @@ -1522,7 +1515,6 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
>  	.link_bit_rate = 25175,
> -	.clock = 25175,
>  	.tx = {  0xbe88, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1548,7 +1540,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
>  	.link_bit_rate = 27000,
> -	.clock = 27000,
>  	.tx = {  0xbe88, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1574,7 +1565,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
>  	.link_bit_rate = 74250,
> -	.clock = 74250,
>  	.tx = {  0xbe88, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1600,7 +1590,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
>  	.link_bit_rate = 148500,
> -	.clock = 148500,
>  	.tx = {  0xbe88, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1626,7 +1615,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
>  	.link_bit_rate = 594000,
> -	.clock = 594000,
>  	.tx = {  0xbe88, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1652,7 +1640,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
>  	.link_bit_rate = 3000000,
> -	.clock = 166670,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1678,7 +1665,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
>  	.link_bit_rate = 6000000,
> -	.clock = 333330,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1704,7 +1690,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
>  	.link_bit_rate = 8000000,
> -	.clock = 444440,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1730,7 +1715,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
>  	.link_bit_rate = 10000000,
> -	.clock = 555560,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -1756,7 +1740,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> 
>  static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
>  	.link_bit_rate = 12000000,
> -	.clock = 666670,
>  	.tx = {  0xbe98, /* tx cfg0 */
>  		  0x9800, /* tx cfg1 */
>  		  0x0000, /* tx cfg2 */
> @@ -2006,7 +1989,6 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_
>  		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
> 
>  	pll_state->link_bit_rate	= pixel_clock;
> -	pll_state->clock	= pixel_clock;
>  	pll_state->tx[0]	= 0xbe88;
>  	pll_state->tx[1]	= 0x9800;
>  	pll_state->tx[2]	= 0x0000;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b3e942f2eeb0..6b348d329957 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1022,8 +1022,7 @@ struct intel_c10pll_state {  };
> 
>  struct intel_c20pll_state {
> -	u32 link_bit_rate;
> -	u32 clock; /* in kHz */
> +	u32 link_bit_rate; /* in kHz */
>  	u16 tx[3];
>  	u16 cmn[4];
>  	union {
> --
> 2.34.1



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