[PATCH] drm/i915: fix display ver 12-13 fault error handling

[Jani Nikula]

On Fri, 08 Dec 2023, Matt Roper <matthew.d.roper at intel.com> wrote:
> On Fri, Dec 08, 2023 at 01:20:08PM +0200, Jani Nikula wrote:
>> Unless I'm completely misreading the bspec, there are no defined bits
>> for plane gtt fault errors in DE PIPE IIR for a display versions
>> 12-14. This would explain why DG2 in the linked bug is getting thousands
>> of fault errors.
>
> I think you might be misreading the spec?  On TGL, bits 7-11 are listed
> as plane1-4+cursor fault status, and bits 20-22 are listed as plane 5-7
> fault status.  Bits 7-11 are tagged with a REMOVEDBY tag that eventually
> drops them for MTL onward, and bits 20-22 are tagged with a REMOVEDBY
> tag that drops them for RKL onward (which makes sense because those
> extra planes stopped existing at that point).
>
> Maybe the bspec's way of displaying things is what's causing the
> confusion?  When you see
>
>         REMOVEDBY(xxxx)
>         [ Foo, Bar, Baz ]
>
> The "Foo, Bar, Baz" platform list is the *remaining* list of platforms
> after the removal is taken into account, not the platforms actually
> being removed.  You can hover over the REMOVEDBY link to see the actual
> platforms being removed and a link to the change record for that.

Yeah. It's not one of the more clear register specs out there. Sorry for
the noise, and thanks for taking the time to explain this.

BR,
Jani.


-- 
Jani Nikula, Intel