[PATCH 3/4] drm/i915/dmc: Also disable HRR event on TGL main DMC

[Ville Syrjälä]

On Wed, Dec 13, 2023 at 10:17:58AM +0200, Imre Deak wrote:
> On Mon, Dec 11, 2023 at 11:37:49PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > Unlike later platforms TGL has the half refresh rate (HRR) event
> > on the main DMC (as opposed to the pipe DMC). Since we're disabling
> > that event on all later platforms already let's do the same on
> > TGL as well.
> > 
> > There is supposedly a bit somewhere (DMC_CHICKEN on TGL) to make
> > the handler not do anything, but we don't currently have code
> > to frob it. Though that bit should be off by default, the ADL+
> > experience has shown us that trusting any of this isn't a good
> > idea. So seems safer to just disable all event handlers we know
> > that we don't need.
> > 
> > Also the TGL DMC firmware is apparently using the wrong event
> > (undelayed vblank) here anyway. It should be using the delayed
> > vblank event instead (like ADL+ firmware does), but they didn't
> > release a firmware fix for this and instead just hacked around
> > this in the Windows driver code :/
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dmc.c      | 5 +++++
> >  drivers/gpu/drm/i915/display/intel_dmc_regs.h | 1 +
> >  2 files changed, 6 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index 9385898e3aa5..0722d322ec63 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -448,6 +448,11 @@ static bool disable_dmc_evt(struct drm_i915_private *i915,
> >  	    REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC)
> >  		return true;
> >  
> > +	/* also disable the HRR event on the main DMC on TGL */
> > +	if (IS_TIGERLAKE(i915) &&
> > +	    REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A)
> 
> The adls FW has the same event (but not the MSEC flip-queue one for some
> reason).

I can't see it in the binary. Though I am using hexdump so it might
also be that I'm looking in the wrong place :P

> 
> > +		return true;
> > +
> >  	return false;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > index cf10094acae3..90d0dbb41cfe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > @@ -60,6 +60,7 @@
> >  
> >  #define DMC_EVT_CTL_EVENT_ID_MASK	REG_GENMASK(15, 8)
> >  #define DMC_EVT_CTL_EVENT_ID_FALSE	0x01
> > +#define DMC_EVT_CTL_EVENT_ID_VBLANK_A	0x32 /* main DMC */
> >  /* An event handler scheduled to run at a 1 kHz frequency. */
> >  #define DMC_EVT_CTL_EVENT_ID_CLK_MSEC	0xbf
> >  
> > -- 
> > 2.41.0
> > 

-- 
Ville Syrjälä
Intel