[Intel-gfx] [PATCH 0/1] Fix logic to get slice_height for dp
Suraj Kandpal
suraj.kandpal at intel.com
Thu Feb 2 11:46:12 UTC 2023
According to bspec :49259 VDSC spec implies that 108 lines is an optimal
slice height, but any size can be used as long as vertical active
integer multiple and maximum vertical slice count requirements are met.
Add a fix in this patch to go for most optimal lines and move ahead from
there instead of primitively using 8 lines.
Suraj Kandpal (1):
drm/i915/dp: Fix logic to fetch slice_height
drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++----------
1 file changed, 17 insertions(+), 11 deletions(-)
--
2.25.1
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