[Intel-gfx] [PATCH 0/1] Fix logic to get slice_height for dp

[Jani Nikula]

On Thu, 02 Feb 2023, Suraj Kandpal <suraj.kandpal at intel.com> wrote:
> According to bspec :49259 VDSC spec implies that 108 lines is an optimal
> slice height, but any size can be used as long as vertical active
> integer multiple and maximum vertical slice count requirements are met.
> Add a fix in this patch to go for most optimal lines and move ahead from
> there instead of primitively using 8 lines.

There's no need for a cover letter if you're sending just one patch.

>
> Suraj Kandpal (1):
>   drm/i915/dp: Fix logic to fetch slice_height
>
>  drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++----------
>  1 file changed, 17 insertions(+), 11 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center