[Intel-gfx] [PATCH 1/2] drm/i915: Populate wm.max_level for everyone

[Jani Nikula]

On Thu, 09 Feb 2023, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Switch ilk+ and skl+ platforms to also setting up
> wm.max_level and remove a bunch of if ladders as a result.
>
> There will be a tiny change in the debugfs on CHV machines
> that have DVFS disabled in the BIOS. Presviously debugfs
> would show the latency for the DVFS level as well, but
> that will no longer be the case. Which is arguably better
> as that number is absolutely meaningless when DVFS can't
> be enabled anyway.

Reviewed-by: Jani Nikula <jani.nikula at intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  .../drm/i915/display/intel_display_debugfs.c   | 18 ++----------------
>  drivers/gpu/drm/i915/display/skl_watermark.c   |  5 +++++
>  drivers/gpu/drm/i915/intel_pm.c                | 18 +++++++-----------
>  3 files changed, 14 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 9e2fb8626c96..b5a2f1a27870 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1288,14 +1288,7 @@ static void wm_latency_show(struct seq_file *m, const u16 wm[8])
>  	int level;
>  	int num_levels;
>  
> -	if (IS_CHERRYVIEW(dev_priv))
> -		num_levels = 3;
> -	else if (IS_VALLEYVIEW(dev_priv))
> -		num_levels = 1;
> -	else if (IS_G4X(dev_priv))
> -		num_levels = 3;
> -	else
> -		num_levels = ilk_wm_max_level(dev_priv) + 1;
> +	num_levels = ilk_wm_max_level(dev_priv) + 1;
>  
>  	drm_modeset_lock_all(&dev_priv->drm);
>  
> @@ -1407,14 +1400,7 @@ static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
>  	int ret;
>  	char tmp[32];
>  
> -	if (IS_CHERRYVIEW(dev_priv))
> -		num_levels = 3;
> -	else if (IS_VALLEYVIEW(dev_priv))
> -		num_levels = 1;
> -	else if (IS_G4X(dev_priv))
> -		num_levels = 3;
> -	else
> -		num_levels = ilk_wm_max_level(dev_priv) + 1;
> +	num_levels = ilk_wm_max_level(dev_priv) + 1;
>  
>  	if (len >= sizeof(tmp))
>  		return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 022aed8dd440..97dc66012bdc 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3258,6 +3258,11 @@ static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
>  
>  static void skl_setup_wm_latency(struct drm_i915_private *i915)
>  {
> +	if (HAS_HW_SAGV_WM(i915))
> +		i915->display.wm.max_level = 5;
> +	else
> +		i915->display.wm.max_level = 7;
> +
>  	if (DISPLAY_VER(i915) >= 14)
>  		mtl_read_wm_latency(i915, i915->display.wm.skl_latency);
>  	else
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e0364c4141b8..3e13b940444a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2836,6 +2836,8 @@ static void hsw_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
>  {
>  	u64 sskpd;
>  
> +	i915->display.wm.max_level = 4;
> +
>  	sskpd = intel_uncore_read64(&i915->uncore, MCH_SSKPD);
>  
>  	wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
> @@ -2851,6 +2853,8 @@ static void snb_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
>  {
>  	u32 sskpd;
>  
> +	i915->display.wm.max_level = 3;
> +
>  	sskpd = intel_uncore_read(&i915->uncore, MCH_SSKPD);
>  
>  	wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);
> @@ -2863,6 +2867,8 @@ static void ilk_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
>  {
>  	u32 mltr;
>  
> +	i915->display.wm.max_level = 2;
> +
>  	mltr = intel_uncore_read(&i915->uncore, MLTR_ILK);
>  
>  	/* ILK primary LP0 latency is 700 ns */
> @@ -2889,17 +2895,7 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
>  
>  int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
>  {
> -	/* how many WM levels are we expecting */
> -	if (HAS_HW_SAGV_WM(dev_priv))
> -		return 5;
> -	else if (DISPLAY_VER(dev_priv) >= 9)
> -		return 7;
> -	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> -		return 4;
> -	else if (DISPLAY_VER(dev_priv) >= 6)
> -		return 3;
> -	else
> -		return 2;
> +	return dev_priv->display.wm.max_level;
>  }
>  
>  void intel_print_wm_latency(struct drm_i915_private *dev_priv,

-- 
Jani Nikula, Intel Open Source Graphics Center