[Intel-gfx] [PATCH v2 5/9] drm/i915/display/mtl: Program latch to phy reset

[Matt Roper]

On Tue, Feb 21, 2023 at 11:35:03PM -0800, Radhakrishna Sripada wrote:
> From: José Roberto de Souza <jose.souza at intel.com>
> 
> Latch reset of phys during DC9 and when driver is unloaded to avoid
> phy reset.
> 
> Specification ask us to program it closer to the step that enables
> DC9 in DC_STATE_EN but doing this way allow us to sanitize the phy
> latch during driver load.
> 
> BSpec: 49197
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
>  drivers/gpu/drm/i915/i915_reg.h                    | 2 ++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 743b919bb2cf..50098c77e3be 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1624,6 +1624,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
>  	intel_power_well_enable(dev_priv, well);
>  	mutex_unlock(&power_domains->lock);
>  
> +	if (DISPLAY_VER(dev_priv) == 14)
> +		intel_de_rmw(dev_priv, DC_STATE_EN,
> +			     HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0);
> +
>  	/* 4. Enable CDCLK. */
>  	intel_cdclk_init_hw(dev_priv);
>  
> @@ -1677,6 +1681,10 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
>  	/* 3. Disable CD clock */
>  	intel_cdclk_uninit_hw(dev_priv);
>  
> +	if (DISPLAY_VER(dev_priv) == 14)
> +		intel_de_rmw(dev_priv, DC_STATE_EN, 0,
> +			     HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH);
> +
>  	/*
>  	 * 4. Disable Power Well 1 (PG1).
>  	 *    The AUX IO power wells are toggled on demand, so they are already
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7c9ac5b43831..fa1905cc5a99 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7360,6 +7360,8 @@ enum skl_power_gate {
>  #define  DC_STATE_DISABLE		0
>  #define  DC_STATE_EN_DC3CO		REG_BIT(30)
>  #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
> +#define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
> +#define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
>  #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
>  #define  DC_STATE_EN_DC9		(1 << 3)
>  #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation