[Intel-gfx] [PATCH] drm/i915/dg2: Add HDMI pixel clock frequencies 267.30 and 319.89 MHz

[Jani Nikula]

On Thu, 23 Feb 2023, "Shankar, Uma" <uma.shankar at intel.com> wrote:
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal at intel.com>
>> Sent: Thursday, February 23, 2023 10:06 AM
>> To: intel-gfx at lists.freedesktop.org
>> Cc: Roper, Matthew D <matthew.d.roper at intel.com>; Shankar, Uma
>> <uma.shankar at intel.com>; Sharma, Swati2 <swati2.sharma at intel.com>
>> Subject: [PATCH] drm/i915/dg2: Add HDMI pixel clock frequencies 267.30 and 319.89
>> MHz
>> 
>> Add snps phy table values for HDMI pixel clocks 267.30 MHz and
>> 319.89 MHz. Values are based on the Bspec algorithm for PLL programming for
>> HDMI.
>
> Looks Good to me.
> Reviewed-by: Uma Shankar <uma.shankar at intel.com>

Needs Cc: stable for some kernels back, when force probe was removed
from DG2. Please check and add while applying.

BR,
Jani.

>
>> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8008
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_snps_phy.c | 62 +++++++++++++++++++
>>  1 file changed, 62 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> index c65c771f5c46..1cfb94b5cedb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> @@ -1419,6 +1419,36 @@ static const struct intel_mpllb_state dg2_hdmi_262750 =
>> {
>>  		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),  };
>> 
>> +static const struct intel_mpllb_state dg2_hdmi_267300 = {
>> +	.clock = 267300,
>> +	.ref_control =
>> +		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
>> +	.mpllb_cp =
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
>> +	.mpllb_div =
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
>> +	.mpllb_div2 =
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
>> +	.mpllb_fracn1 =
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
>> +	.mpllb_fracn2 =
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 30146) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36699),
>> +	.mpllb_sscen =
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), };
>> +
>>  static const struct intel_mpllb_state dg2_hdmi_268500 = {
>>  	.clock = 268500,
>>  	.ref_control =
>> @@ -1509,6 +1539,36 @@ static const struct intel_mpllb_state dg2_hdmi_241500 =
>> {
>>  		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),  };
>> 
>> +static const struct intel_mpllb_state dg2_hdmi_319890 = {
>> +	.clock = 319890,
>> +	.ref_control =
>> +		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
>> +	.mpllb_cp =
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
>> +	.mpllb_div =
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
>> +	.mpllb_div2 =
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
>> +	.mpllb_fracn1 =
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
>> +	.mpllb_fracn2 =
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 64094) |
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13631),
>> +	.mpllb_sscen =
>> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), };
>> +
>>  static const struct intel_mpllb_state dg2_hdmi_497750 = {
>>  	.clock = 497750,
>>  	.ref_control =
>> @@ -1696,8 +1756,10 @@ static const struct intel_mpllb_state * const
>> dg2_hdmi_tables[] = {
>>  	&dg2_hdmi_209800,
>>  	&dg2_hdmi_241500,
>>  	&dg2_hdmi_262750,
>> +	&dg2_hdmi_267300,
>>  	&dg2_hdmi_268500,
>>  	&dg2_hdmi_296703,
>> +	&dg2_hdmi_319890,
>>  	&dg2_hdmi_497750,
>>  	&dg2_hdmi_592000,
>>  	&dg2_hdmi_593407,
>> --
>> 2.25.1
>

-- 
Jani Nikula, Intel Open Source Graphics Center