[Intel-gfx] [PATCH v2] drm/i915/gen12: Update combo PHY init sequence

[Matt Atwood]

On Tue, Feb 21, 2023 at 12:18:36PM -0800, Matt Roper wrote:
> The bspec was updated with a minor change to the 'DCC mode select'
> setting to be programmed during combo PHY initialization.
> 
> v2:
>  - Keep the opencoded rmw behavior instead of switching to
>    intel_de_rmw().  We need to read from a _LN register, but write to
>    the _GRP register to update all lanes.
> 
> Bspec: 49291
Reviewed-by: Matt Atwood <matthew.s.atwood at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_combo_phy.c      | 5 ++---
>  drivers/gpu/drm/i915/display/intel_combo_phy_regs.h | 4 ++--
>  2 files changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 27e98eabb006..922a6d87b553 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -233,8 +233,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
>  				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
>  
>  		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
> -				     DCC_MODE_SELECT_MASK,
> -				     DCC_MODE_SELECT_CONTINUOSLY);
> +				     DCC_MODE_SELECT_MASK, RUN_DCC_ONCE);
>  	}
>  
>  	ret &= icl_verify_procmon_ref_values(dev_priv, phy);
> @@ -354,7 +353,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
>  
>  			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
>  			val &= ~DCC_MODE_SELECT_MASK;
> -			val |= DCC_MODE_SELECT_CONTINUOSLY;
> +			val |= RUN_DCC_ONCE;
>  			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
>  		}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
> index 2ed65193ca19..b0983edccf3f 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
> @@ -90,8 +90,8 @@
>  #define ICL_PORT_PCS_DW1_AUX(phy)		_MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
>  #define ICL_PORT_PCS_DW1_GRP(phy)		_MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
>  #define ICL_PORT_PCS_DW1_LN(ln, phy)		_MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
> -#define   DCC_MODE_SELECT_MASK			(0x3 << 20)
> -#define   DCC_MODE_SELECT_CONTINUOSLY		(0x3 << 20)
> +#define   DCC_MODE_SELECT_MASK			REG_GENMASK(21, 20)
> +#define   RUN_DCC_ONCE				REG_FIELD_PREP(DCC_MODE_SELECT_MASK, 0)
>  #define   COMMON_KEEPER_EN			(1 << 26)
>  #define   LATENCY_OPTIM_MASK			(0x3 << 2)
>  #define   LATENCY_OPTIM_VAL(x)			((x) << 2)
> -- 
> 2.39.1
>