[Intel-gfx] [PATCH 1/2] drm/i915: Whitelist COMMON_SLICE_CHICKEN3 for UMD access

[Gustavo Sousa]

On Thu, Feb 23, 2023 at 04:22:59PM -0800, Matt Roper wrote:
> A recommended tuning setting for both gen12 and Xe_HP platforms requires
> that we grant userspace r/w access to the COMMON_SLICE_CHICKEN3
> register.
> 
> Bspec: 73993, 73994, 31870, 68331
> Cc: Dongwon Kim <dongwon.kim at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>

Reviewed-by: Gustavo Sousa <gustavo.jo.sousa at gmail.com>

> ---
> The bspec update to add COMMON_SLICE_CHICKEN3 to the tuning guide pages
> is still pending at the moment, but should be finalized shortly.
> 
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++++-
>  1 file changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 1ef9c9fa2eff..0444c715998a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2194,6 +2194,10 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
>  
>  		/* Wa_1806527549:tgl */
>  		whitelist_reg(w, HIZ_CHICKEN);
> +
> +		/* Required by recommended tuning setting (not a workaround) */
> +		whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3);
> +
>  		break;
>  	default:
>  		break;
> @@ -2227,6 +2231,9 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine)
>  					  RING_FORCE_TO_NONPRIV_ACCESS_RD |
>  					  RING_FORCE_TO_NONPRIV_RANGE_4);
>  
> +		/* Required by recommended tuning setting (not a workaround) */
> +		whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);
> +
>  		break;
>  	case COMPUTE_CLASS:
>  		/* Wa_16011157294:dg2_g10 */
> @@ -2264,6 +2271,22 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine)
>  	blacklist_trtt(engine);
>  }
>  
> +static void mtl_whitelist_build(struct intel_engine_cs *engine)
> +{
> +	struct i915_wa_list *w = &engine->whitelist;
> +
> +	switch (engine->class) {
> +	case RENDER_CLASS:
> +		/* Required by recommended tuning setting (not a workaround) */
> +		whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);
> +
> +		break;
> +	default:
> +		break;
> +	}
> +
> +}
> +
>  void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *i915 = engine->i915;
> @@ -2272,7 +2295,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>  	wa_init_start(w, engine->gt, "whitelist", engine->name);
>  
>  	if (IS_METEORLAKE(i915))
> -		; /* noop; none at this time */
> +		mtl_whitelist_build(engine);
>  	else if (IS_PONTEVECCHIO(i915))
>  		pvc_whitelist_build(engine);
>  	else if (IS_DG2(i915))
> -- 
> 2.39.1
>