[Intel-gfx] [PATCH v2] drm/i915/display: Implement Wa_14015648006

[Jani Nikula]

On Wed, 04 Jan 2023, Jouni Högander <jouni.hogander at intel.com> wrote:
> Add 4th pipe and extend TGL Wa_16013835468 to support ADLP, MTL and
> DG2 and all TGL steppings.

Please prefix the subject with "drm/i915/psr" instead of the overly
generic "display".

>
> BSpec: 54369, 55378, 66624
>
> v2:
>  - apply for PSR1 as well
>  - remove stepping information from comments
>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: José Roberto de Souza <jose.souza at intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
>

Nitpick, while at it, please no blank lines between tags.

Both of the above can be fixed while applying if there's no other reason
to resend the patch.

BR,
Jani.

> Signed-off-by: Mika Kahola <mika.kahola at intel.com>
> Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 48 ++++++++++++++----------
>  drivers/gpu/drm/i915/i915_reg.h          |  1 +
>  2 files changed, 29 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index d0d774219cc5..507f810d4a4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1112,6 +1112,8 @@ static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
>  		return LATENCY_REPORTING_REMOVED_PIPE_B;
>  	case PIPE_C:
>  		return LATENCY_REPORTING_REMOVED_PIPE_C;
> +	case PIPE_D:
> +		return LATENCY_REPORTING_REMOVED_PIPE_D;
>  	default:
>  		MISSING_CASE(intel_dp->psr.pipe);
>  		return 0;
> @@ -1163,6 +1165,23 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  			     intel_dp->psr.psr2_sel_fetch_enabled ?
>  			     IGNORE_PSR2_HW_TRACKING : 0);
>  
> +	/*
> +	 * Wa_16013835468
> +	 * Wa_14015648006
> +	 */
> +	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	    IS_DISPLAY_VER(dev_priv, 12, 13)) {
> +		u16 vtotal, vblank;
> +
> +		vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal -
> +			crtc_state->uapi.adjusted_mode.crtc_vdisplay;
> +		vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end -
> +			crtc_state->uapi.adjusted_mode.crtc_vblank_start;
> +		if (vblank > vtotal)
> +			intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
> +				     wa_16013835468_bit_get(intel_dp));
> +	}
> +
>  	if (intel_dp->psr.psr2_enabled) {
>  		if (DISPLAY_VER(dev_priv) == 9)
>  			intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
> @@ -1196,20 +1215,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  		else if (IS_ALDERLAKE_P(dev_priv))
>  			intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
>  				     CLKGATE_DIS_MISC_DMASC_GATING_DIS);
> -
> -		/* Wa_16013835468:tgl[b0+], dg1 */
> -		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
> -		    IS_DG1(dev_priv)) {
> -			u16 vtotal, vblank;
> -
> -			vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal -
> -				 crtc_state->uapi.adjusted_mode.crtc_vdisplay;
> -			vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end -
> -				 crtc_state->uapi.adjusted_mode.crtc_vblank_start;
> -			if (vblank > vtotal)
> -				intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
> -					     wa_16013835468_bit_get(intel_dp));
> -		}
>  	}
>  }
>  
> @@ -1362,6 +1367,15 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>  
> +	/*
> +	 * Wa_16013835468
> +	 * Wa_14015648006
> +	 */
> +	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> +	    IS_DISPLAY_VER(dev_priv, 12, 13))
> +		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> +			     wa_16013835468_bit_get(intel_dp), 0);
> +
>  	if (intel_dp->psr.psr2_enabled) {
>  		/* Wa_16011168373:adl-p */
>  		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> @@ -1377,12 +1391,6 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  		else if (IS_ALDERLAKE_P(dev_priv))
>  			intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
>  				     CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
> -
> -		/* Wa_16013835468:tgl[b0+], dg1 */
> -		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
> -		    IS_DG1(dev_priv))
> -			intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> -				     wa_16013835468_bit_get(intel_dp), 0);
>  	}
>  
>  	intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8b2cf980f323..b0b3b511e19f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5737,6 +5737,7 @@
>  #define  RESET_PCH_HANDSHAKE_ENABLE	REG_BIT(4)
>  
>  #define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
> +#define   LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
>  #define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
>  #define   LATENCY_REPORTING_REMOVED_PIPE_C	REG_BIT(25)
>  #define   LATENCY_REPORTING_REMOVED_PIPE_B	REG_BIT(24)

-- 
Jani Nikula, Intel Open Source Graphics Center