[Intel-gfx] [PATCH] drm/i915/gt: Cover rest of SVG unit MCR registers

[Matt Roper]

On Thu, Jan 05, 2023 at 10:37:01AM -0300, Gustavo Sousa wrote:
> CHICKEN_RASTER_{1,2} got overlooked with the move done in a9e69428b1b4
> ("drm/i915: Define MCR registers explicitly"). Registers from the SVG
> unit became multicast as of Xe_HP graphics.
> 
> BSpec: 66534
> Fixes: a9e69428b1b4 ("drm/i915: Define MCR registers explicitly").
> Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>

Applied to drm-intel-gt-next.  Thanks for the patch.


Matt


> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 4 ++--
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index f8eb807b56f9..570699548c77 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -407,10 +407,10 @@
>  #define GEN9_WM_CHICKEN3			_MMIO(0x5588)
>  #define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
>  
> -#define CHICKEN_RASTER_1			_MMIO(0x6204)
> +#define CHICKEN_RASTER_1			MCR_REG(0x6204)
>  #define   DIS_SF_ROUND_NEAREST_EVEN		REG_BIT(8)
>  
> -#define CHICKEN_RASTER_2			_MMIO(0x6208)
> +#define CHICKEN_RASTER_2			MCR_REG(0x6208)
>  #define   TBIMR_FAST_CLIP			REG_BIT(5)
>  
>  #define VFLSKPD					MCR_REG(0x62a8)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index bf84efb3f15f..9a40aa61e86e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -645,7 +645,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>  				   struct i915_wa_list *wal)
>  {
> -	wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
> +	wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
>  	wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
>  			     REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
>  	wa_mcr_add(wal,
> @@ -780,7 +780,7 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>  		wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
>  
>  	/* Wa_15010599737:dg2 */
> -	wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
> +	wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
>  
>  	/* Wa_18019271663:dg2 */
>  	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
> -- 
> 2.39.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation