[Intel-gfx] [PATCH] drm/i915: Move/adjust register definitions related to Wa_22011450934

[Gustavo Sousa]

On Tue, Jan 17, 2023 at 12:26:27PM -0800, Matt Roper wrote:
> The implementation of Wa_22011450934 introduced three new register
> definitions in i915_reg.h that didn't get moved to the GT/engine
> register headers when all the other registers moved; let's move them to
> the appropriate headers and tidy up their definitions now for
> consistency:
> 
>  - STATE_ACK_DEBUG is moved to the engine register header and converted
>    to a parameterized definition; the workaround only needs the RCS
>    instance to be programmed, but there are instances on other engines
>    that could be used by other workarounds in the future.
> 
>  - The two CULLBIT registers move to the GT register header.  Since
>    they belong to MMIO ranges that became MCR starting with Xe_HP,
>    their definitions should be defined as MCR_REG() and use an Xe_HP
>    prefix to keep the register semantics clear.
> 
> Note that the MCR definition is just for consistency and to prevent
> accidental misuse if other workarounds related to these registers show
> up in the future.  There's no functional change to today's driver since
> the workaround that references these registers only accesses them via
> MI_LRR engine instructions.  Engine-initiated register accesses do not
> utilize the same same steering controls as CPU-initiated accesses; they
> use a different steering control register (0x20CC) which is initialized
> to a non-terminated DSS target by pre-OS firmware and never changed
> thereafter (i915 does not touch it and userspace does not have
> permission to change that register).
> 
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa at intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_regs.h | 1 +
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 4 ++++
>  drivers/gpu/drm/i915/gt/intel_lrc.c         | 6 +++---
>  drivers/gpu/drm/i915/i915_reg.h             | 4 ----
>  4 files changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
> index ee3efd06ee54..6b9d9f837669 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
> @@ -81,6 +81,7 @@
>  #define RING_EIR(base)				_MMIO((base) + 0xb0)
>  #define RING_EMR(base)				_MMIO((base) + 0xb4)
>  #define RING_ESR(base)				_MMIO((base) + 0xb8)
> +#define GEN12_STATE_ACK_DEBUG(base)		_MMIO((base) + 0xbc)
>  #define RING_INSTPM(base)			_MMIO((base) + 0xc0)
>  #define RING_CMD_CCTL(base)			_MMIO((base) + 0xc4)
>  #define ACTHD(base)				_MMIO((base) + 0xc8)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 4f5c06d60bcd..4a4bab261e66 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -407,6 +407,8 @@
>  #define GEN9_WM_CHICKEN3			_MMIO(0x5588)
>  #define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
>  
> +#define XEHP_CULLBIT1				MCR_REG(0x6100)
> +
>  #define CHICKEN_RASTER_1			MCR_REG(0x6204)
>  #define   DIS_SF_ROUND_NEAREST_EVEN		REG_BIT(8)
>  
> @@ -457,6 +459,8 @@
>  #define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE	REG_BIT(13)
>  #define   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	REG_BIT(3)
>  
> +#define XEHP_CULLBIT2				MCR_REG(0x7030)
> +
>  #define GEN8_L3CNTLREG				_MMIO(0x7034)
>  #define   GEN8_ERRDETBCTRL			(1 << 9)
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 7771a19008c6..1dffe392b95c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1351,16 +1351,16 @@ static u32 *
>  dg2_emit_rcs_hang_wabb(const struct intel_context *ce, u32 *cs)
>  {
>  	*cs++ = MI_LOAD_REGISTER_IMM(1);
> -	*cs++ = i915_mmio_reg_offset(GEN12_STATE_ACK_DEBUG);
> +	*cs++ = i915_mmio_reg_offset(GEN12_STATE_ACK_DEBUG(ce->engine->mmio_base));
>  	*cs++ = 0x21;
>  
>  	*cs++ = MI_LOAD_REGISTER_REG;
>  	*cs++ = i915_mmio_reg_offset(RING_NOPID(ce->engine->mmio_base));
> -	*cs++ = i915_mmio_reg_offset(GEN12_CULLBIT1);
> +	*cs++ = i915_mmio_reg_offset(XEHP_CULLBIT1);
>  
>  	*cs++ = MI_LOAD_REGISTER_REG;
>  	*cs++ = i915_mmio_reg_offset(RING_NOPID(ce->engine->mmio_base));
> -	*cs++ = i915_mmio_reg_offset(GEN12_CULLBIT2);
> +	*cs++ = i915_mmio_reg_offset(XEHP_CULLBIT2);
>  
>  	return cs;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8b2cf980f323..d30443f06bdd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8113,10 +8113,6 @@ enum skl_power_gate {
>  #define CLKGATE_DIS_MISC			_MMIO(0x46534)
>  #define  CLKGATE_DIS_MISC_DMASC_GATING_DIS	REG_BIT(21)
>  
> -#define GEN12_CULLBIT1			_MMIO(0x6100)
> -#define GEN12_CULLBIT2			_MMIO(0x7030)
> -#define GEN12_STATE_ACK_DEBUG		_MMIO(0x20BC)
> -
>  #define _MTL_CLKGATE_DIS_TRANS_A			0x604E8
>  #define _MTL_CLKGATE_DIS_TRANS_B			0x614E8
>  #define MTL_CLKGATE_DIS_TRANS(trans)			_MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A)
> -- 
> 2.39.0
>