[Intel-gfx] [PATCH v3 1/3] drm/i915/dsc: Move rc param calculation for native_420

[Nautiyal, Ankit K]

On 7/3/2023 3:42 PM, Suraj Kandpal wrote:
> Move rc_param calculation for native_420 into calculate_rc_parameter.
> second_line_bpg_offset and second_line_offset_adj are both rc params
> and it would be better to have these calculated where all the other
> rc parameters are calculated.
>
> --v2
> -Add the reason for commit in commit message [Jani]
>
> --v3
> -Move nsl_second_line_bpg_offset with the other 420 calculation
> in calculate_rc_param [Ankit]
>
> Cc: Jani Nikula <jani.nikula at linux.intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vdsc.c | 45 ++++++++++++-----------
>   1 file changed, 24 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index bd9116d2cd76..7d0edb440ca6 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -78,6 +78,27 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
>   	else
>   		vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
>   
> +	/* According to DSC 1.2 specs in Section 4.1 if native_420 is set:

Start comment from next line, as per comment format.

Otherwise LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

> +	 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
> +	 * height < 8.
> +	 * -second_line_offset_adj is 512 as shown by emperical values to yield best chroma
> +	 * preservation in second line.
> +	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
> +	 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
> +	 * fractional bits.
> +	 */
> +	if (vdsc_cfg->native_420) {
> +		if (vdsc_cfg->slice_height >= 8)
> +			vdsc_cfg->second_line_bpg_offset = 12;
> +		else
> +			vdsc_cfg->second_line_bpg_offset =
> +				2 * (vdsc_cfg->slice_height - 1);
> +
> +		vdsc_cfg->second_line_offset_adj = 512;
> +		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
> +							vdsc_cfg->slice_height - 1);
> +	}
> +
>   	/* Our hw supports only 444 modes as of today */
>   	if (bpp >= 12)
>   		vdsc_cfg->initial_offset = 2048;
> @@ -190,30 +211,12 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>   	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
>   
>   	/*
> -	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set:
> -	 * -We need to double the current bpp.
> -	 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
> -	 * height < 8.
> -	 * -second_line_offset_adj is 512 as shown by emperical values to yeild best chroma
> -	 * preservation in second line.
> -	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
> -	 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
> -	 * fractional bits.
> +	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set
> +	 * we need to double the current bpp.
>   	 */
> -	if (vdsc_cfg->native_420) {
> +	if (vdsc_cfg->native_420)
>   		vdsc_cfg->bits_per_pixel <<= 1;
>   
> -		if (vdsc_cfg->slice_height >= 8)
> -			vdsc_cfg->second_line_bpg_offset = 12;
> -		else
> -			vdsc_cfg->second_line_bpg_offset =
> -				2 * (vdsc_cfg->slice_height - 1);
> -
> -		vdsc_cfg->second_line_offset_adj = 512;
> -		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
> -							vdsc_cfg->slice_height - 1);
> -	}
> -
>   	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>   
>   	drm_dsc_set_rc_buf_thresh(vdsc_cfg);