[Intel-gfx] [PATCH 1/8] drm/i915: Consolidate condition for Wa_22011802037

[Gustavo Sousa]

Quoting Matt Roper (2023-07-18 19:27:55-03:00)
>The workaround bounds for Wa_22011802037 are somewhat complex and are
>replicated in several places throughout the code.  Pull the condition
>out to a helper function to prevent mistakes if this condition needs to
>change again in the future.
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa at intel.com>

>---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c      |  4 +---
> .../drm/i915/gt/intel_execlists_submission.c   |  4 +---
> drivers/gpu/drm/i915/gt/intel_reset.c          | 18 ++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_reset.h          |  2 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c         |  4 +---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c  |  4 +---
> 6 files changed, 24 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>index 0aff5bb13c53..0d095337b350 100644
>--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>@@ -1616,9 +1616,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
>          * Wa_22011802037: Prior to doing a reset, ensure CS is
>          * stopped, set ring stop bit and prefetch disable bit to halt CS
>          */
>-        if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>-            (GRAPHICS_VER(engine->i915) >= 11 &&
>-            GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>+        if (intel_engine_reset_needs_wa_22011802037(engine->gt))
>                 intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
>                                       _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
> 
>diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>index d85b5a6d981f..b9f297c546fb 100644
>--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>@@ -3001,9 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
>          * Wa_22011802037: In addition to stopping the cs, we need
>          * to wait for any pending mi force wakeups
>          */
>-        if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>-            (GRAPHICS_VER(engine->i915) >= 11 &&
>-            GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>+        if (intel_engine_reset_needs_wa_22011802037(engine->gt))
>                 intel_engine_wait_for_pending_mi_fw(engine);
> 
>         engine->execlists.reset_ccid = active_ccid(engine);
>diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>index cc6bd21a3e51..1ff7b42521c9 100644
>--- a/drivers/gpu/drm/i915/gt/intel_reset.c
>+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>@@ -1632,6 +1632,24 @@ void __intel_fini_wedge(struct intel_wedge_me *w)
>         w->gt = NULL;
> }
> 
>+/*
>+ * Wa_22011802037 requires that we (or the GuC) ensure that no command
>+ * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
>+ */
>+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
>+{
>+        if (GRAPHICS_VER(gt->i915) < 11)
>+                return false;
>+
>+        if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
>+                return true;
>+
>+        if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
>+                return false;
>+
>+        return true;
>+}
>+
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> #include "selftest_reset.c"
> #include "selftest_hangcheck.c"
>diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
>index 25c975b6e8fc..f615b30b81c5 100644
>--- a/drivers/gpu/drm/i915/gt/intel_reset.h
>+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
>@@ -78,4 +78,6 @@ void __intel_fini_wedge(struct intel_wedge_me *w);
> bool intel_has_gpu_reset(const struct intel_gt *gt);
> bool intel_has_reset_engine(const struct intel_gt *gt);
> 
>+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt);
>+
> #endif /* I915_RESET_H */
>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>index 2eb891b270ae..1e532981f74e 100644
>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>@@ -292,9 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>                 flags |= GUC_WA_DUAL_QUEUE;
> 
>         /* Wa_22011802037: graphics version 11/12 */
>-        if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>-            (GRAPHICS_VER(gt->i915) >= 11 &&
>-            GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
>+        if (intel_engine_reset_needs_wa_22011802037(gt))
>                 flags |= GUC_WA_PRE_PARSER;
> 
>         /* Wa_16011777198:dg2 */
>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>index a0e3ef1c65d2..1bd5d8f7c40b 100644
>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>@@ -1658,9 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
>          * Wa_22011802037: In addition to stopping the cs, we need
>          * to wait for any pending mi force wakeups
>          */
>-        if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>-            (GRAPHICS_VER(engine->i915) >= 11 &&
>-             GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
>+        if (intel_engine_reset_needs_wa_22011802037(engine->gt)) {
>                 intel_engine_stop_cs(engine);
>                 intel_engine_wait_for_pending_mi_fw(engine);
>         }
>-- 
>2.41.0
>