[Intel-gfx] [PATCH] drm/i915/dp: Fix LT debug print in SDP CRC enable

Borah, Chaitanya Kumar chaitanya.kumar.borah at intel.com
Fri Jul 28 09:18:11 UTC 2023


Hello Arun,

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Arun R
> Murthy
> Sent: Friday, July 14, 2023 11:08 AM
> To: intel-gfx at lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH] drm/i915/dp: Fix LT debug print in SDP CRC enable
> 
> The debug print for enabling SDP CRC16 is applicable only for DP2.0, 

DP2.0 and UHBR?

>but this
> debug print was not within the uhbr check and was always printed.
> Fis this by adding proper checks and returning.

Typo.

> 
> Signed-off-by: Arun R Murthy <arun.r.murthy at intel.com>
> ---
>  .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 +++++++-----
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index a263773f4d68..4485ef4f8ec6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1390,11 +1390,13 @@ void intel_dp_128b132b_sdp_crc16(struct
> intel_dp *intel_dp,
>  	 * Default value of bit 31 is '0' hence discarding the write
>  	 * TODO: Corrective actions on SDP corruption yet to be defined
>  	 */
> -	if (intel_dp_is_uhbr(crtc_state))
> -		/* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
> -		drm_dp_dpcd_writeb(&intel_dp->aux,
> -
> DP_SDP_ERROR_DETECTION_CONFIGURATION,
> -				   DP_SDP_CRC16_128B132B_EN);
> +	if (!intel_dp_is_uhbr(crtc_state))
> +		return;

I see that while calling this function in intel_ddi_pre_enable_dp(), we do have a
check for for DP2.0

if (HAS_DP20(dev_priv))
		intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
					    crtc_state);

Should this check be added within the function too for the sake of completion?

Regards

Chaitanya

> +
> +	/* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
> +	drm_dp_dpcd_writeb(&intel_dp->aux,
> +			   DP_SDP_ERROR_DETECTION_CONFIGURATION,
> +			   DP_SDP_CRC16_128B132B_EN);
> 
>  	lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b
> enabled\n");  }
> --
> 2.25.1



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