[Intel-gfx] [PATCH v4 03/14] drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines

[Srivatsa, Anusha]

> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane at intel.com>
> Sent: Wednesday, July 26, 2023 1:07 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: Ursulin, Tvrtko <tvrtko.ursulin at intel.com>; jani.nikula at linux.intel.com;
> Srivatsa, Anusha <anusha.srivatsa at intel.com>; Atwood, Matthew S
> <matthew.s.atwood at intel.com>; Roper, Matthew D
> <matthew.d.roper at intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane at intel.com>; Srivatsa, Anusha
> <anusha.srivatsa at intel.com>
> Subject: [PATCH v4 03/14] drm/i915/skl: s/SKL/SKYLAKE for
> platform/subplatform defines
> 
> Follow consistent naming convention. Replace SKL with SKYLAKE and Replace
> IS_SKL_GRAPHICS_STEP with
> IS_SKYLAKE() && IS_GRAPHICS_STEP().
> 
> v2:
> - Change subject skl instead of SKL(Anusha)
> 
> v3:
> - Unrolled wrapper IS_SKL_GRAPHICS_STEP.
> - Replace with IS_PLATFORM && DISPLAY_STEP(tvrtko/jani)
> 
> v4:
> - Removed the unused macro.
> 
> Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane at intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa at intel.com>

> 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
>  drivers/gpu/drm/i915/gt/intel_workarounds.c        |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h                    | 13 ++++++-------
>  3 files changed, 9 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 5b2665a9d86d..e85eab21b09d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1746,9 +1746,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder
> *encoder)
>  		encoder->get_buf_trans = kbl_u_get_buf_trans;
>  	} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) ||
> IS_KABYLAKE(i915)) {
>  		encoder->get_buf_trans = kbl_get_buf_trans;
> -	} else if (IS_SKL_ULX(i915)) {
> +	} else if (IS_SKYLAKE_ULX(i915)) {
>  		encoder->get_buf_trans = skl_y_get_buf_trans;
> -	} else if (IS_SKL_ULT(i915)) {
> +	} else if (IS_SKYLAKE_ULT(i915)) {
>  		encoder->get_buf_trans = skl_u_get_buf_trans;
>  	} else if (IS_SKYLAKE(i915)) {
>  		encoder->get_buf_trans = skl_get_buf_trans; diff --git
> a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9634ab8d738b..b0b7d448364a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1192,7 +1192,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
>  		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
> 
>  	/* WaInPlaceDecompressionHang:skl */
> -	if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
> +	if (IS_SKYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, STEP_A0,
> +STEP_H0))
>  		wa_write_or(wal,
>  			    GEN9_GAMT_ECO_REG_RW_IA,
>  			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6607f233461a..d7f7ca135000 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -609,19 +609,19 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
>  /* ULX machines are also considered ULT. */  #define IS_HASWELL_ULX(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) -
> #define IS_SKL_ULT(i915) \
> +#define IS_SKYLAKE_ULT(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) -
> #define IS_SKL_ULX(i915) \
> +#define IS_SKYLAKE_ULX(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
> #define IS_KBL_ULT(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
> #define IS_KBL_ULX(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
> -#define IS_SKL_GT2(i915)	(IS_SKYLAKE(i915) && \
> +#define IS_SKYLAKE_GT2(i915)	(IS_SKYLAKE(i915) && \
>  				 INTEL_INFO(i915)->gt == 2)
> -#define IS_SKL_GT3(i915)	(IS_SKYLAKE(i915) && \
> +#define IS_SKYLAKE_GT3(i915)	(IS_SKYLAKE(i915) && \
>  				 INTEL_INFO(i915)->gt == 3)
> -#define IS_SKL_GT4(i915)	(IS_SKYLAKE(i915) && \
> +#define IS_SKYLAKE_GT4(i915)	(IS_SKYLAKE(i915) && \
>  				 INTEL_INFO(i915)->gt == 4)
>  #define IS_KBL_GT2(i915)	(IS_KABYLAKE(i915) && \
>  				 INTEL_INFO(i915)->gt == 2)
> @@ -649,7 +649,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_TGL_UY(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
> 
> -#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) &&
> IS_GRAPHICS_STEP(p, since, until))
> 
>  #define IS_KBL_GRAPHICS_STEP(i915, since, until) \
>  	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until)) @@ -
> 800,7 +799,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> 
>  /* WaRsDisableCoarsePowerGating:skl,cnl */
>  #define NEEDS_WaRsDisableCoarsePowerGating(i915)			\
> -	(IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
> +	(IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
> 
>  /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
>   * rows, which changed the alignment requirements and fence programming.
> --
> 2.34.1