[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: Restore HSW/BDW PSR1 (rev2)
Patchwork
patchwork at emeril.freedesktop.org
Fri Jun 9 16:04:50 UTC 2023
== Series Details ==
Series: drm/i915/psr: Restore HSW/BDW PSR1 (rev2)
URL : https://patchwork.freedesktop.org/series/116814/
State : warning
== Summary ==
Error: dim checkpatch failed
8d0ed154f842 drm/i915: Re-init clock gating on coming out of PC8+
611fbc172ab6 drm/i915/psr: Fix BDW PSR AUX CH data register offsets
-:26: WARNING:LONG_LINE_COMMENT: line length of 111 exceeds 100 columns
#26: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:84:
+#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */
total: 0 errors, 1 warnings, 0 checks, 8 lines checked
36f425356759 drm/i915/psr: Wrap PSR1 register with functions
-:142: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#142: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1242:
+ intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder)) & EDP_PSR_ENABLE);
total: 0 errors, 1 warnings, 0 checks, 208 lines checked
52de64b78bab drm/i915/psr: Reintroduce HSW PSR1 registers
54a96841affe drm/i915/psr: Bring back HSW/BDW PSR AUX CH registers/setup
5e417ac7e0c0 drm/i915/psr: HSW/BDW have no PSR2
c00c783fa2b5 drm/i915/psr: Restore PSR interrupt handler for HSW
1eb8ab4d74fc drm/i915/psr: Implement WaPsrDPAMaskVBlankInSRD:hsw
9f0f594fd35d drm/i915/psr: Implement WaPsrDPRSUnmaskVBlankInSRD:hsw
9477cb0f2f4e drm/i915/psr: Do no mask display register writes on hsw/bdw
b75d4b981cb5 drm/i915/psr: Don't skip both TP1 and TP2/3 on hsw/bdw
8493c9e3d192 drm/i915/psr: Allow PSR with sprite enabled on hsw/bdw
7921951d6576 drm/i915/psr: Re-enable PSR1 on hsw/bdw
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