[Intel-gfx] [PATCH v2] drm/i915: Extend Wa_14015795083 platforms

[Kalvala, Haridhar]

On 6/17/2023 4:20 AM, Matt Roper wrote:
> This workaround was already implemented for DG2, PVC, and some steppings
> of MTL, but the workaround database has now been updated to extend this
> workaround to TGL, RKL, DG1, and ADL.
>
> v2:
>   - Skip readback verification for these extra gen12lp platforms.  On
>     some of the platforms, the firmware locks this register, preventing
>     the driver from making any modifications.  We should still try to
>     apply the workaround, but if the register is locked and the value
>     doesn't stick, that's semi-expected and not something we want to flag
>     as a driver error on debug builds.

Hi Matt,

Looks good to me.

Reviewed-by: Haridhar Kalvala <haridhar.kalvala at intel.com>

> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4d2dece96011..4bb83c435a70 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1485,6 +1485,18 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>   
>   	/* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
>   	wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
> +
> +	/*
> +	 * Wa_14015795083
> +	 *
> +	 * Firmware on some gen12 platforms locks the MISCCPCTL register,
> +	 * preventing i915 from modifying it for this workaround.  Skip the
> +	 * readback verification for this workaround on debug builds; if the
> +	 * workaround doesn't stick due to firmware behavior, it's not an error
> +	 * that we want CI to flag.
> +	 */
> +	wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,
> +	       0, 0, false);
>   }
>   
>   static void

-- 
Regards,
Haridhar Kalvala