[Intel-gfx] [PATCH 1/1] drm/i915/display: HDMI2.0/DP1p62Gbps skew violation when there is skew between DL PCLK

[Mitul Golani]

When doing type-C PHY voltage swing programming for HDMI and
DP 1.62Gbps, program DKLP_PCS_GLUE_TX_DPCNTL2[loadgen_sharing_pmd_disable]
to '1'. For other DP frequencies, program
DKLP_PCS_GLUE_TX_DPCNTL2[loadgen_sharing_pmd_disable] to '0'.

This Workaround is specific to Display Version 13

Wa_15010727533

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani at intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 13 +++++++++++++
 drivers/gpu/drm/i915/i915_reg.h          |  6 ++++++
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 61722556bb47..5a6f048f4f1c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1362,6 +1362,19 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
 				  DKL_TX_DP20BITMODE, 0);
 
+		if (DISPLAY_VER(dev_priv) == 13) {
+			if ((crtc_state->port_clock == 594000 &&
+			    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) ||
+			    (crtc_state->port_clock == 162000 &&
+			    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))) {
+				intel_de_rmw(dev_priv, DKLP_TX_DPCNTL2(tc_port),
+					     LOADGEN_SHARING_PMD_DISABLE, 1);
+			} else {
+				intel_de_rmw(dev_priv, DKLP_TX_DPCNTL2(tc_port),
+					     LOADGEN_SHARING_PMD_DISABLE, 0);
+			}
+		}
+
 		if (IS_ALDERLAKE_P(dev_priv)) {
 			u32 val;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dcf64e32cd54..5487301d4ad3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6663,4 +6663,10 @@ enum skl_power_gate {
 
 #define MTL_MEDIA_GSI_BASE		0x380000
 
+#define _DKLP_PCS_GLUE_TX_DPCNTL2	0xB68
+#define LOADGEN_SHARING_PMD_DISABLE	REG_BIT(2)
+#define DKLP_TX_DPCNTL2(tc_port)	_MMIO(_PORT(tc_port, \
+						    _DKL_PHY1_BASE, \
+						    _DKL_PHY2_BASE) + \
+						    _DKLP_PCS_GLUE_TX_DPCNTL2)
 #endif /* _I915_REG_H_ */
-- 
2.25.1