[Intel-gfx] [PATCH 1/3] drm/i915: Don't switch to TPS1 when disabling DP_TP_CTL

[Imre Deak]

On Tue, Feb 14, 2023 at 03:43:46PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> AFAICS Bspec has never asked us to switch to TPS1 when *disabling*
> DP_TP_CTL. Let's stop doing that in case it confuses something.
> We do have to switch before we *enable* DP_TP_CTL, but that
> is already being handled correctly.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Imre Deak <imre.deak at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bfd1e30a27b4..4af2ba2dfcad 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2624,8 +2624,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
>  
>  	if (intel_crtc_has_dp_encoder(crtc_state)) {
>  		val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
> -		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> -		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> +		val &= ~DP_TP_CTL_ENABLE;
>  		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
>  	}
>  
> @@ -3153,8 +3152,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>  			wait = true;
>  		}
>  
> -		dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> -		dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
> +		dp_tp_ctl &= ~DP_TP_CTL_ENABLE;
>  		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
>  		intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
>  
> -- 
> 2.39.1
>