[Intel-gfx] [PATCH 3/3] drm/i915: Fix idle pattern enabling

[Imre Deak]

On Tue, Feb 14, 2023 at 03:43:48PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Currently we are always switching to the idle pattern after the
> link training, but we don't always wait for the minimum number
> of idle patterns sent. That doesn't look to be what Bspec
> asks of us.
> 
> According to bspec what we should do is switch to idle pattern
> and wait for it only in DP1.4 MST cases. In all other cases we
> should apparently do neither.
> 
> What confuses matters further is that the port sync SST sequence
> asks us to "stay in idle pattern". But if we never switched to it
> how can we stay in it? This still needs further clarificaiton.

HSW seems to require it also for SST, but yes for all other platforms
bspec only requires it for MST. The DP2.1 standard has some addition
(3.5.1.2.6) referring to idle pattern to be sent after TPS even for SST.
Not sure if this would be done automatically by HW w/o manually
switching to it.

> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 20 +++++++++-----------
>  1 file changed, 9 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4af2ba2dfcad..a3466b71d18a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3219,24 +3219,22 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
>  {
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum port port = encoder->port;
>  	u32 val;
>  
> +	/*
> +	 * FIXME DP modeset sequence says to switch to idle pattern
> +	 * only for DP1.4 MST cases, but port sync SST sequence asks
> +	 * us to "stay in Idle Pattern", implying that we should
> +	 * switch to it earlier. Which is it?
> +	 */
> +	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
> +		return;
> +
>  	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
>  	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
>  	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
>  	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
>  
> -	/*
> -	 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
> -	 * reason we need to set idle transmission mode is to work around a HW
> -	 * issue where we enable the pipe while not in idle link-training mode.
> -	 * In this case there is requirement to wait for a minimum number of
> -	 * idle patterns to be sent.
> -	 */
> -	if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
> -		return;
> -
>  	if (intel_de_wait_for_set(dev_priv,
>  				  dp_tp_status_reg(encoder, crtc_state),
>  				  DP_TP_STATUS_IDLE_DONE, 1))
> -- 
> 2.39.1
>