[Intel-gfx] [PATCH 3/9] drm/i915: Define more pipe timestamp registers

[Hogander, Jouni]

On Tue, 2023-03-14 at 15:02 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Add definitions for various pipe timestamp registers:
> - frame timestamp (last start of vblank) (g4x+), already had this
> defined
> - flip timestamp (when SURF was last written) (g4x+)
> - flipdone timestamp (when last flipdone was signalled) (tgl+)
> 
> Note that on pre-tgl the flip related timestamps are only updated
> for primary plane flips, but on tgl+ we can select which plane
> updates them (via PIPE_MISC2). Let's define those related bits
> as well.
> 
> Curiously VLV/CHV do not have the frame/flip timestamp registers,
> despite all the other related registers being inherited from g4x.
> This means we can get rid of the pipe_offsets[] usage for these,
> and thus the implicit dev_priv is gone as well.

According to bspec these exist in VLV (Bspec: 8264, 8261) ?

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index a383397ebeca..66b6f451b80a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3526,6 +3526,8 @@
>  #define   PIPE_MISC2_BUBBLE_COUNTER_MASK       REG_GENMASK(31, 24)
>  #define  
> PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN  REG_FIELD_PREP(PIPE_MISC2_BUBBLE
> _COUNTER_MASK, 80)
>  #define  
> PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE
> _COUNTER_MASK, 20)
> +#define  
> PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK          REG_GENMASK(2, 0) /*
> tgl+ */
> +#define  
> PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)     REG_FIELD_PREP(PIPE_MISC
> 2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
>  #define PIPE_MISC2(pipe)               _MMIO_PIPE(pipe,
> _PIPE_MISC2_A, _PIPE_MISC2_B)
>  
>  /* Skylake+ pipe bottom (background) color */
> @@ -7545,9 +7547,23 @@ enum skl_power_gate {
>  #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT  12
>  #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK   (0xf
> << 12)
>  
> +/* g4x+, except vlv/chv! */
>  #define _PIPE_FRMTMSTMP_A              0x70048
> +#define _PIPE_FRMTMSTMP_B              0x71048
>  #define PIPE_FRMTMSTMP(pipe)           \
> -                       _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
> +       _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
> +
> +/* g4x+, except vlv/chv! */
> +#define _PIPE_FLIPTMSTMP_A             0x7004C
> +#define _PIPE_FLIPTMSTMP_B             0x7104C
> +#define PIPE_FLIPTMSTMP(pipe)          \
> +       _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
> +
> +/* tgl+ */

This is mentioned in pre tgl documentation as well? (Bspec: 29591)

> +#define _PIPE_FLIPDONETMSTMP_A         0x70054
> +#define _PIPE_FLIPDONETMSTMP_B         0x71054
> +#define PIPE_FLIPDONETIMSTMP(pipe)     \
> +       _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A,
> _PIPE_FLIPDONETMSTMP_B)
>  
>  #define GGC                            _MMIO(0x108040)
>  #define   GMS_MASK                     REG_GENMASK(15, 8)

BR,

Jouni Högander