[Intel-gfx] [PATCH v2 1/2] drm/i915: Sanitycheck MMIO access early in driver load

Andi Shyti andi.shyti at linux.intel.com
Tue Mar 21 17:15:33 UTC 2023


> We occasionally see the PCI device in a non-accessible state at the
> point the driver is loaded.  When this happens, all BAR accesses will
> read back as 0xFFFFFFFF.  Rather than reading registers and
> misinterpreting their (invalid) values, let's specifically check for
> 0xFFFFFFFF in a register that cannot have that value to see if the
> device is accessible.
> 
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Signed-off-by: Andi Shyti <andi.shyti at linux.intel.com>

Reviewed-by: Andi Shyti <andi.shyti at linux.intel.com>

Andi


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