[Intel-gfx] [PATCH v7 08/10] dt-bindings: msm/dp: Add bindings for HDCP registers
Mark Yacoub
markyacoub at chromium.org
Fri Mar 24 19:55:52 UTC 2023
From: Sean Paul <seanpaul at chromium.org>
Add the bindings for the MSM DisplayPort HDCP registers
which are required to write the HDCP key into the display controller as
well as the registers to enable HDCP authentication/key
exchange/encryption.
Cc: Rob Herring <robh at kernel.org>
Cc: Stephen Boyd <swboyd at chromium.org>
Reviewed-by: Rob Herring <robh at kernel.org>
Signed-off-by: Sean Paul <seanpaul at chromium.org>
Signed-off-by: Mark Yacoub <markyacoub at chromium.org>
---
Changes in v2:
-Drop register range names (Stephen)
-Fix yaml errors (Rob)
Changes in v3:
-Add new compatible string for dp-hdcp
-Add descriptions to reg
-Add minItems/maxItems to reg
-Make reg depend on the new hdcp compatible string
Changes in v4:
-Rebase on Bjorn's multi-dp patchset
Changes in v4.5:
-Remove maxItems from reg (Rob)
-Remove leading zeros in example (Rob)
Changes in v5:
-None
Changes in v6:
-Rebased: modify minItems instead of adding it as new line.
Changes in v7:
-Revert the change to minItems
-Added the maxItems to Reg
.../devicetree/bindings/display/msm/dp-controller.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index 774ccb5184b88..c47ade3a4ae17 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -31,6 +31,8 @@ properties:
- description: link register block
- description: p0 register block
- description: p1 register block
+ - description: (Optional) Registers for HDCP device key injection
+ - description: (Optional) Registers for HDCP TrustZone interaction
interrupts:
maxItems: 1
@@ -158,6 +160,7 @@ allOf:
aux-bus: false
reg:
minItems: 5
+ maxItems: 7
required:
- "#sound-dai-cells"
@@ -175,7 +178,9 @@ examples:
<0xae90200 0x200>,
<0xae90400 0xc00>,
<0xae91000 0x400>,
- <0xae91400 0x400>;
+ <0xae91400 0x400>,
+ <0xaed1000 0x174>,
+ <0xaee1000 0x2c>;
interrupt-parent = <&mdss>;
interrupts = <12>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
--
2.40.0.348.gf938b09366-goog
More information about the Intel-gfx
mailing list