[Intel-gfx] [PATCH 1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers

[Juha-Pekka Heikkila]

On 10.5.2023 16.15, Jani Nikula wrote:
> On Tue, 09 May 2023, Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com> wrote:
>> Add Tile4 type ccs modifiers with aux buffer needed for MTL
> 
> Please send this Cc: dri-devel too.

Sure, I'll resend shortly. Here I just didn't want to spam dri-devel 
since from original set this patch is already sent there and didn't get 
any changes since that.

/Juha-Pekka

> 
>>
>> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
>> ---
>>   include/uapi/drm/drm_fourcc.h | 43 +++++++++++++++++++++++++++++++++++
>>   1 file changed, 43 insertions(+)
>>
>> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>> index de703c6be969..cbe214adf1e4 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -657,6 +657,49 @@ extern "C" {
>>    */
>>   #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
>>   
>> +/*
>> + * Intel color control surfaces (CCS) for display ver 14 render compression.
>> + *
>> + * The main surface is tile4 and at plane index 0, the CCS is linear and
>> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
>> + * main surface. In other words, 4 bits in CCS map to a main surface cache
>> + * line pair. The main surface pitch is required to be a multiple of four
>> + * tile4 widths.
>> + */
>> +#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
>> +
>> +/*
>> + * Intel color control surfaces (CCS) for display ver 14 media compression
>> + *
>> + * The main surface is tile4 and at plane index 0, the CCS is linear and
>> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
>> + * main surface. In other words, 4 bits in CCS map to a main surface cache
>> + * line pair. The main surface pitch is required to be a multiple of four
>> + * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
>> + * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
>> + * planes 2 and 3 for the respective CCS.
>> + */
>> +#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
>> +
>> +/*
>> + * Intel Color Control Surface with Clear Color (CCS) for display ver 14 render
>> + * compression.
>> + *
>> + * The main surface is tile4 and is at plane index 0 whereas CCS is linear
>> + * and at index 1. The clear color is stored at index 2, and the pitch should
>> + * be ignored. The clear color structure is 256 bits. The first 128 bits
>> + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
>> + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
>> + * the converted clear color of size 64 bits. The first 32 bits store the Lower
>> + * Converted Clear Color value and the next 32 bits store the Higher Converted
>> + * Clear Color value when applicable. The Converted Clear Color values are
>> + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
>> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
>> + * corresponds to an area of 4x1 tiles in the main surface. The main surface
>> + * pitch is required to be a multiple of 4 tile widths.
>> + */
>> +#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
>> +
>>   /*
>>    * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>>    *
>