[Intel-gfx] [PATCH v2 7/7] drm/i915: Define more PS_CTRL bits

[Luca Coelho]

On Thu, 2023-05-11 at 14:54 +0300, Ville Syrjälä wrote:
> On Thu, May 11, 2023 at 10:29:01AM +0300, Luca Coelho wrote:
> > On Wed, 2023-04-26 at 16:50 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > 
> > > To avoid annoying spec lookups let's define more PS_CTRL
> > > bits in the header.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
> > >  1 file changed, 11 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index f5ae8d1eb6ff..e08bb15eddcf 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4055,6 +4055,9 @@
> > >  #define _PS_2B_CTRL      0x68A80
> > >  #define _PS_1C_CTRL      0x69180
> > >  #define   PS_SCALER_EN				REG_BIT(31)
> > > +#define   PS_SCALER_TYPE_MASK			REG_BIT(30) /* icl+ */
> > > +#define   PS_SCALER_TYPE_NON_LINEAR		REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
> > > +#define   PS_SCALER_TYPE_LINEAR			REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
> > >  #define   SKL_PS_SCALER_MODE_MASK		REG_GENMASK(29, 28) /* skl/bxt */
> > >  #define   SKL_PS_SCALER_MODE_DYN		REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
> > >  #define   SKL_PS_SCALER_MODE_HQ			REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
> > > @@ -4062,6 +4065,7 @@
> > >  #define   PS_SCALER_MODE_MASK			REG_BIT(29) /* glk-tgl */
> > >  #define   PS_SCALER_MODE_NORMAL			REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
> > >  #define   PS_SCALER_MODE_PLANAR			REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
> > > +#define   PS_ADAPTIVE_FILTERING_EN		REG_BIT(28) /* icl+ */
> > >  #define   PS_BINDING_MASK			REG_GENMASK(27, 25)
> > >  #define   PS_BINDING_PIPE			REG_FIELD_PREP(PS_BINDING_MASK, 0)
> > >  #define   PS_BINDING_PLANE(plane_id)		REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
> > > @@ -4070,8 +4074,15 @@
> > >  #define   PS_FILTER_PROGRAMMED			REG_FIELD_PREP(PS_FILTER_MASK, 1)
> > >  #define   PS_FILTER_EDGE_ENHANCE		REG_FIELD_PREP(PS_FILTER_MASK, 2)
> > >  #define   PS_FILTER_BILINEAR			REG_FIELD_PREP(PS_FILTER_MASK, 3)
> > > +#define   PS_ADAPTIVE_FILTER_MASK		REG_BIT(22) /* icl+ */
> > > +#define   PS_ADAPTIVE_FILTER_MEDIUM		REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
> > > +#define   PS_ADAPTIVE_FILTER_EDGE_ENHANCE	REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
> > > +#define   PS_PIPE_SCALER_LOC_MASK		REG_BIT(21) /* icl+ */
> > > +#define   PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC	REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
> > > +#define   PS_PIPE_SCALER_LOC_AFTER_CSC		REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
> > >  #define   PS_VERT3TAP				REG_BIT(21) /* skl/bxt */
> > >  #define   PS_VERT_INT_INVERT_FIELD		REG_BIT(20)
> > > +#define   PS_PROG_SCALE_FACTOR			REG_BIT(19) /* tgl+ */
> > 
> > This one is actually a two-bit field, isn't it? 19:18.  And why not
> > define the values for it here too, like with the previous ones?
> 
> It's still a single bit in current hardware.

Oh, sorry, I checked the wrong specs.  In that case:

Reviewed-by: Luca Coelho <luciano.coelho at intel.com>

--
Cheers,
Luca.