[Intel-gfx] [PATCH v2] drm/i915/gt: drop dependency on VLV_DISPLAY_BASE

[Ville Syrjälä]

On Thu, May 11, 2023 at 06:21:53PM +0300, Jani Nikula wrote:
> CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
> intel_gt_regs.h, is in the gcfgmmio unit, but is technically in the VLV
> display base area.
> 
> Add VLV_GUNIT_BASE to drop dependency on VLV_DISPLAY_BASE and thus
> display/intel_display_reg_defs.h in intel_gt_regs.h.
> 
> v2: Add VLV_GUNIT_BASE (Ville)
> 
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index b8a39c219b60..718cb2c80f79 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -7,7 +7,8 @@
>  #define __INTEL_GT_REGS__
>  
>  #include "i915_reg_defs.h"
> -#include "display/intel_display_reg_defs.h"	/* VLV_DISPLAY_BASE */
> +
> +#define VLV_GUNIT_BASE			0x180000
>  
>  /*
>   * The perf control registers are technically multicast registers, but the
> @@ -1469,7 +1470,7 @@
>  #define GEN12_RCU_MODE				_MMIO(0x14800)
>  #define   GEN12_RCU_MODE_CCS_ENABLE		REG_BIT(0)
>  
> -#define CHV_FUSE_GT				_MMIO(VLV_DISPLAY_BASE + 0x2168)
> +#define CHV_FUSE_GT				_MMIO(VLV_GUNIT_BASE + 0x2168)
>  #define   CHV_FGT_DISABLE_SS0			(1 << 10)
>  #define   CHV_FGT_DISABLE_SS1			(1 << 11)
>  #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT		16
> -- 
> 2.39.2

-- 
Ville Syrjälä
Intel