[Intel-gfx] [PATCH v2 2/2] drm/i915/mtl: Add MTL performance tuning changes

[Gustavo Sousa]

Quoting Kalvala, Haridhar (2023-05-14 08:13:10)
>
>On 5/13/2023 7:44 AM, Radhakrishna Sripada wrote:
>> MTL reuses the tuning parameters for DG2. Extend the dg2
>> performance tuning parameters to MTL.
>>
>> v2: Add DRAW_WATERMARK tuning parameter.
>>
>> Bspec: 68331
>> Cc: Haridhar Kalvala <haridhar.kalvala at intel.com>
>> Cc: Matt Roper <matthew.d.roper at intel.com>
>> Cc: Gustavo Sousa <gustavo.sousa at intel.com>
>> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++--
>>   1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 786349e95487..72dab970de5b 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -817,6 +817,10 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>   {
>>           struct drm_i915_private *i915 = engine->i915;
>>   
>> +        dg2_ctx_gt_tuning_init(engine, wal);
>> +
>> +        wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
>
>Hi RK,
>
>I am not sure but have doubt w.r.t DRAW_WATERMARK are we not doing same 
>in [ Patch V2 1/2].
>
>Thank you,
>
>Haridhar Kalvala

Yeah, I think this should be executed only for B0+ steps.

--
Gustavo Sousa

>
>> +
>>           if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>               IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>                   /* Wa_14014947963 */
>> @@ -1754,7 +1758,7 @@ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
>>                   wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
>>           }
>>   
>> -        if (IS_DG2(gt->i915)) {
>> +        if (IS_DG2(gt->i915) || IS_METEORLAKE(gt->i915)) {
>>                   wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
>>                   wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
>>           }
>> @@ -2944,7 +2948,7 @@ static void
>>   add_render_compute_tuning_settings(struct drm_i915_private *i915,
>>                                      struct i915_wa_list *wal)
>>   {
>> -        if (IS_DG2(i915))
>> +        if (IS_DG2(i915) || IS_METEORLAKE(i915))
>>                   wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
>>   
>>           /*
>
>-- 
>Regards,
>Haridhar Kalvala
>