[Intel-gfx] [PATCH] drm/i915/mtl: do not enable render power-gating on MTL

[Das, Nirmoy]

On 5/17/2023 3:59 PM, Andrzej Hajda wrote:
> Multiple CI tests fails with forcewake ack timeouts
> if render power gating is enabled.
> BSpec 52698 clearly states it should be 0 for MTL.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4983
> Signed-off-by: Andrzej Hajda <andrzej.hajda at intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 908a3d0f2343f4..ebb2373dd73640 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -117,8 +117,9 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>   			GEN6_RC_CTL_RC6_ENABLE |
>   			GEN6_RC_CTL_EI_MODE(1);
>   
> -	/* Wa_16011777198 - Render powergating must remain disabled */
> -	if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
> +	/* Wa_16011777198 and BSpec 52698 - Render powergating must be off */

Nice catch! instead of bspec you could add Wa_14012655556.


> +	if (IS_METEORLAKE(gt->i915) ||
> +	    IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
>   	    IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
>   		pg_enable =
>   			GEN9_MEDIA_PG_ENABLE |
>
> ---
> base-commit: 01d3dd92d1b71421f6ee85e1bea829e0a917d979
> change-id: 20230517-mtl_disable_render_pg-b9f9f1567f9e

^ unwanted artifacts ?   Otherwise this looks good to me.

Reviewed-by: Nirmoy Das <nirmoy.das at intel.com>

>
> Best regards,