[Intel-gfx] [PATCH v6 6/7] drm/i915/pmu: Prepare for multi-tile non-engine counters

[Dixit, Ashutosh]

On Wed, 17 May 2023 13:55:41 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>
> Reserve some bits in the counter config namespace which will carry the
> tile id and prepare the code to handle this.
>
> No per tile counters have been added yet.
>
> v2:
> - Fix checkpatch issues
> - Use 4 bits for gt id in non-engine counters. Drop FIXME.
> - Set MAX GTs to 4. Drop FIXME.
>
> v3: (Ashutosh, Tvrtko)
> - Drop BUG_ON that would never fire
> - Make enable u64
> - Pull in some code from next patch
>
> v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko)
>
> v5: s/u64/u32 where needed (Ashutosh)

Reviewed-by: Ashutosh Dixit <ashutosh.dixit at intel.com>