[Intel-gfx] [PATCH] drm/i915/xelpmp: Add Wa_16021867713

[Gustavo Sousa]

Quoting Matt Roper (2023-11-06 17:07:21-03:00)
>On Mon, Nov 06, 2023 at 04:46:27PM -0300, Gustavo Sousa wrote:
>> This workaround applies to all steppings of Xe_LPM+. Implement the KMD
>> part.
>> 
>> Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
>> ---
>>  drivers/gpu/drm/i915/gt/intel_engine_regs.h |  3 +++
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 ++++++++++++++
>>  2 files changed, 17 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
>> index c0c8c12edea1..7060ce4fe058 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
>> @@ -260,6 +260,9 @@
>>  #define VDBOX_CGCTL3F10(base)                        _MMIO((base) + 0x3f10)
>>  #define   IECPUNIT_CLKGATE_DIS                        REG_BIT(22)
>>  
>> +#define VDBOX_CGCTL3F1C(base)                        _MMIO((base) + 0x3f1c)
>> +#define   MFXPIPE_CLKGATE_DIS                        REG_BIT(3)
>> +
>>  #define VDBOX_CGCTL3F18(base)                        _MMIO((base) + 0x3f18)
>>  #define   ALNUNIT_CLKGATE_DIS                        REG_BIT(13)
>
>Nitpick:  3f1c should be sorted after 3f18 to keep the registers in
>order.

Oops.

>
>Aside from that,
>
>Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

Thanks! I just sent a v2.

--
Gustavo Sousa

>
>
>>  
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 12859b8d2092..63205edfea50 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -1662,9 +1662,23 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>>          debug_dump_steering(gt);
>>  }
>>  
>> +static void
>> +wa_16021867713(struct intel_gt *gt, struct i915_wa_list *wal)
>> +{
>> +        struct intel_engine_cs *engine;
>> +        int id;
>> +
>> +        for_each_engine(engine, gt, id)
>> +                if (engine->class == VIDEO_DECODE_CLASS)
>> +                        wa_write_or(wal, VDBOX_CGCTL3F1C(engine->mmio_base),
>> +                                    MFXPIPE_CLKGATE_DIS);
>> +}
>> +
>>  static void
>>  xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>>  {
>> +        wa_16021867713(gt, wal);
>> +
>>          /*
>>           * Wa_14018778641
>>           * Wa_18018781329
>> -- 
>> 2.42.0
>> 
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation