[Intel-gfx] [PATCH v2 0/1] drm/i915/xe2lpd: WA for underruns during FBC enable

[Vinod Govindapillai]

Update the FBC enabling sequence. The plane binding register bits
need to programmed before fbe enable bit.

v2: update the patch subject and description as this underrun is not
    tied to PSR. FIFO underruns are observed when FBC is enabled on
    plane other than the primary.

Vinod Govindapillai (1):
  drm/i915/xe2lpd: implement WA for underruns while enabling FBC

 drivers/gpu/drm/i915/display/intel_fbc.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

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2.34.1