[Intel-gfx] [PATCH v3 1/1] drm/i915/xe2lpd: implement WA for underruns while enabling FBC

[Vinod Govindapillai]

FIFO underruns are observed when FBC is enabled on plane 2 or 3.
This is root caused to a HW bug and the recommended WA is to
update the FBC enabling sequence. The plane binding register
bits need to be updated separately before programming the FBC
enable bit.

HSD: 16021232047
Signed-off-by: Vinod Govindapillai <vinod.govindapillai at intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index bde12fe62275..8a3594e4d992 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -608,6 +608,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
 static void ivb_fbc_activate(struct intel_fbc *fbc)
 {
 	struct drm_i915_private *i915 = fbc->i915;
+	u32 dpfc_ctl;
 
 	if (DISPLAY_VER(i915) >= 10)
 		glk_fbc_program_cfb_stride(fbc);
@@ -617,8 +618,18 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
 	if (intel_gt_support_legacy_fencing(to_gt(i915)))
 		snb_fbc_program_fence(fbc);
 
+	/*
+	 * xe2lpd: WA for FIFO underruns while enabling FBC on planes 2 or 3
+	 * 1.Write FBC_CTL with Plane binding set correctly with FBC enable = 0
+	 * 2.Write FBC_CTL with Plane binding set correctly with FBC enable = 1
+	 * HSD: 16021232047
+	 */
+	dpfc_ctl = ivb_dpfc_ctl(fbc);
+	if (DISPLAY_VER(i915) >= 20)
+		intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
+
 	intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
-		       DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
+		       DPFC_CTL_EN | dpfc_ctl);
 }
 
 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
-- 
2.34.1