[Intel-gfx] [PATCH 1/4] drm/i915/dp: Account for channel coding efficiency on UHBR links

[Jani Nikula]

On Mon, 13 Nov 2023, Imre Deak <imre.deak at intel.com> wrote:
> Apply the correct BW allocation overhead and channel coding efficiency
> on UHBR link rates, similarly to DP1.4 link rates.
>
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 10 ----------
>  1 file changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 3effafcbb411a..24aebdb715e7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2398,16 +2398,6 @@ add_bw_alloc_overhead(int link_clock, int bw_overhead,
>  	int ch_coding_efficiency =
>  		drm_dp_bw_channel_coding_efficiency(is_uhbr);

Why do we have this and intel_dp_max_data_rate() separately?

BR,
Jani.


>  
> -	/*
> -	 * TODO: adjust for actual UHBR channel coding efficiency and BW
> -	 * overhead.
> -	 */
> -	if (is_uhbr) {
> -		*data_m = pixel_data_rate;
> -		*data_n = link_data_rate * 8 / 10;
> -		return;
> -	}
> -
>  	*data_m = DIV_ROUND_UP_ULL(mul_u32_u32(pixel_data_rate, bw_overhead),
>  				   1000000);
>  	*data_n = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_data_rate, ch_coding_efficiency),

-- 
Jani Nikula, Intel