[Intel-gfx] [PATCH 06/10] drm/i915/spi: spi register with mtd

[Miquel Raynal]

Hi Alexander,

+ Michael and Tudor

Folks, any interesting thought about the below discussion?

alexander.usyskin at intel.com wrote on Tue, 14 Nov 2023 08:47:34 +0000:

> >   
> > > > > > > +	spi->mtd.writesize = SZ_1; /* 1 byte granularity */  
> > > > > >
> > > > > > You say writesize should be aligned with 4 in your next patch?  
> > > > >
> > > > > We support unaligned write by reading aligned 4bytes,
> > > > > replacing changed bytes there and writing whole 4bytes back.
> > > > > Is there any problem with this approach?  
> > > >
> > > > Is there a reason to do that manually rather than letting the core
> > > > handle the complexity?
> > > >  
> > > I was not aware that core can do this. The core implements above logic
> > > if I put SZ_4 here and caller try to write, say, one byte?
> > > And sync multiple writers?
> > > If so, I can remove manual work, I think, and make the patches smaller.  
> > 
> > I haven't checked in detail but I would expect this yes. Please have a
> > round of tests and if it works, please simplify this part.
> > 
> > Thanks,
> > Miquèl  
> 
> When I put SZ_4 here the "mtd_debug info /dev/mtd0" prints "mtd.writesize = 4",
> but "mtd_debug write /dev/mtd0 128 1 c" passes one byte to
> i915_spi_write (mtd._write callback).
> I suppose that mtd subsystem do not support this.
> Or I did something wrong?
> 


Thanks,
Miquèl