[Intel-gfx] [PATCH] drm/i915/dg2: Wa_18028616096 now applies to all DG2

[Gustavo Sousa]

Quoting Matt Roper (2023-11-15 15:21:18-03:00)
>The workaround database was just updated to extend this workaround to
>DG2-G11 (whereas previously it applied only to G10 and G12).
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa at intel.com>

>---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index 63205edfea50..9bc0654efdc0 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -2937,6 +2937,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>                  * Wa_22015475538:dg2
>                  */
>                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
>+
>+                /* Wa_18028616096 */
>+                wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3);
>         }
> 
>         if (IS_DG2_G11(i915)) {
>@@ -2965,11 +2968,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>                            true);
>         }
> 
>-        if (IS_DG2_G10(i915) || IS_DG2_G12(i915)) {
>-                /* Wa_18028616096 */
>-                wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3);
>-        }
>-
>         if (IS_XEHPSDV(i915)) {
>                 /* Wa_1409954639 */
>                 wa_mcr_masked_en(wal,
>-- 
>2.41.0
>